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Searched refs:CFG (Results 1 – 6 of 6) sorted by relevance

/qemu/hw/adc/
H A Dzynq-xadc.c25 CFG = 0x000 / 4, enumerator
85 extract32(s->regs[CFG], CFG_DFIFOTH_SHIFT, CFG_DFIFOTH_LENGTH)) { in zynq_xadc_update_ints()
96 s->regs[CFG] = 0x14 << CFG_IGAP_SHIFT | in zynq_xadc_reset()
139 case CFG: in zynq_xadc_check_offset()
167 case CFG: in zynq_xadc_read()
205 case CFG: in zynq_xadc_write()
206 s->regs[CFG] = val; in zynq_xadc_write()
/qemu/hw/dma/
H A Dxlnx-zynq-devcfg.c84 REG32(CFG, 0x08)
85 FIELD(CFG, RFIFO_TH, 10, 2)
86 FIELD(CFG, WFIFO_TH, 8, 2)
87 FIELD(CFG, RCLK_EDGE, 7, 1)
88 FIELD(CFG, WCLK_EDGE, 6, 1)
89 FIELD(CFG, DISABLE_SRC_INC, 5, 1)
90 FIELD(CFG, DISABLE_DST_INC, 4, 1)
/qemu/hw/nvram/
H A Dxlnx-zynqmp-efuse.c42 REG32(CFG, 0x4)
43 FIELD(CFG, SLVERR_ENABLE, 5, 1)
44 FIELD(CFG, MARGIN_RD, 2, 2)
45 FIELD(CFG, PGM_EN, 1, 1)
46 FIELD(CFG, EFUSE_CLK_SEL, 0, 1)
414 if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) { in zynqmp_efuse_pgm_addr_postw()
H A Dxlnx-versal-efuse-ctrl.c40 REG32(CFG, 0x4)
41 FIELD(CFG, SLVERR_ENABLE, 5, 1)
42 FIELD(CFG, MARGIN_RD, 2, 1)
43 FIELD(CFG, PGM_EN, 1, 1)
388 if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) { in efuse_pgm_locked()
/qemu/target/microblaze/
H A Dtranslate.c269 #define DO_TYPEA_CFG(NAME, CFG, SE, FN) \ argument
271 { return dc->cfg->CFG && do_typea(dc, a, SE, FN); }
277 #define DO_TYPEA0_CFG(NAME, CFG, SE, FN) \ argument
279 { return dc->cfg->CFG && do_typea0(dc, a, SE, FN); }
285 #define DO_TYPEBI_CFG(NAME, CFG, SE, FNI) \ argument
287 { return dc->cfg->CFG && do_typeb_imm(dc, a, SE, FNI); }
/qemu/docs/specs/
H A Dfw_cfg.rst119 Register returns 0x51454d5520434647 (``QEMU CFG`` in big-endian format).