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Searched refs:CP0C1_WR (Results 1 – 3 of 3) sorted by relevance

/qemu/target/mips/
H A Dcpu-defs.c.inc33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
479 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
599 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
620 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
648 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
677 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
704 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
725 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
749 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
789 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
[all …]
H A Dcpu.h870 #define CP0C1_WR 3 macro
/qemu/target/mips/tcg/
H A Dtranslate.c5819 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
5837 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
6553 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
6571 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
7295 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
7313 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
8014 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmtc0()
8032 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmtc0()