Home
last modified time | relevance | path

Searched refs:CP0C4_M (Results 1 – 3 of 3) sorted by relevance

/qemu/target/mips/
H A Dcpu-defs.c.inc49 ((0 << CP0C4_M))
383 .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
408 .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
441 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
485 (3 << CP0C4_IE) | (1U << CP0C4_M),
525 (2 << CP0C4_IE) | (1U << CP0C4_M),
755 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
795 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
906 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
1002 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
H A Dcpu.h915 #define CP0C4_M 31 macro
H A Dkvm.c401 #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M)