Searched refs:CP0C5_MSAEn (Results 1 – 5 of 5) sorted by relevance
34 env->CP0_Config5 |= 1 << CP0C5_MSAEn; in msa_reset()
447 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |759 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |799 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |911 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
392 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { in compute_hflags()
933 #define CP0C5_MSAEn 27 macro
402 #define KVM_REG_MIPS_CP0_CONFIG5_MASK ((1U << CP0C5_MSAEn) | \