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Searched refs:CP0Ca_IP_mask (Results 1 – 5 of 5) sorted by relevance

/qemu/hw/mips/
H A Dmips_int.c51 if (env->CP0_Cause & CP0Ca_IP_mask) { in cpu_mips_irq_request()
/qemu/target/mips/
H A Dinternal.h188 pending = env->CP0_Cause & CP0Ca_IP_mask; in cpu_mips_hw_interrupts_pending()
189 status = env->CP0_Status & CP0Ca_IP_mask; in cpu_mips_hw_interrupts_pending()
H A Dcpu.h818 #define CP0Ca_IP_mask 0x0000FF00 macro
/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c1139 old, old & env->CP0_Cause & CP0Ca_IP_mask, in helper_mtc0_status()
1140 val, val & env->CP0_Cause & CP0Ca_IP_mask, in helper_mtc0_status()
H A Dtlb_helper.c1138 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP; in mips_cpu_do_interrupt()