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Searched refs:CP0SRSC0_SRS2 (Results 1 – 2 of 2) sorted by relevance

/qemu/target/mips/
H A Dcpu.h708 #define CP0SRSC0_SRS2 10 macro
H A Dcpu-defs.c.inc302 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),