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Searched refs:CP0SRSC0_SRS3 (Results 1 – 2 of 2) sorted by relevance

/qemu/target/mips/
H A Dcpu.h707 #define CP0SRSC0_SRS3 20 macro
H A Dcpu-defs.c.inc301 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |