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Searched refs:CP0SRSC2_SRS8 (Results 1 – 2 of 2) sorted by relevance

/qemu/target/mips/
H A Dcpu.h720 #define CP0SRSC2_SRS8 10 macro
H A Dcpu-defs.c.inc308 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),