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Searched refs:CSR_STIMECMPH (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h210 #define CSR_STIMECMPH 0x15D macro
H A Dcsr.c4737 [CSR_STIMECMPH] = { "stimecmph", sstc_32, read_stimecmph, write_stimecmph,