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Searched refs:CXL_COMPONENT_REG_BAR_IDX (Results 1 – 5 of 5) sorted by relevance

/qemu/include/hw/cxl/
H A Dcxl.h22 #define CXL_COMPONENT_REG_BAR_IDX 0 macro
/qemu/hw/pci-bridge/
H A Dcxl_downstream.c127 .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX, in build_dvsecs()
185 pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX, in cxl_dsp_realize()
H A Dcxl_root_port.c138 .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX, in build_dvsecs()
183 pci_register_bar(pci_dev, CXL_COMPONENT_REG_BAR_IDX, in cxl_rp_realize()
H A Dcxl_upstream.c130 .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX, in build_dvsecs()
330 pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX, in cxl_usp_realize()
/qemu/hw/mem/
H A Dcxl_type3.c326 .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX, in build_dvsecs()
683 pci_dev, CXL_COMPONENT_REG_BAR_IDX, in ct3_realize()