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Searched refs:D (Results 1 – 25 of 119) sorted by relevance

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/qemu/crypto/
H A Dxts.c39 D->u[0] = S1->u[0] ^ S2->u[0]; in xts_uint128_xor()
40 D->u[1] = S1->u[1] ^ S2->u[1]; in xts_uint128_xor()
133 xts_uint128 *D = (xts_uint128 *)dst; in xts_decrypt() local
138 xts_uint128 D; in xts_decrypt() local
142 xts_tweak_encdec(datactx, decfunc, &D, &D, &T); in xts_decrypt()
151 xts_uint128 S, D; in xts_decrypt() local
170 memcpy(dst, &D, XTS_BLOCK_SIZE); in xts_decrypt()
214 xts_uint128 D; in xts_encrypt() local
218 xts_tweak_encdec(datactx, encfunc, &D, &D, &T); in xts_encrypt()
228 xts_uint128 S, D; in xts_encrypt() local
[all …]
/qemu/target/loongarch/tcg/
H A Dvec_helper.c462 muls64(&l, &h, Vj->D(i), Vk->D(i)); in HELPER()
463 Vd->D(i) = h; in HELPER()
481 mulu64(&l, &h, Vj->D(i), Vk->D(i)); in HELPER()
482 Vd->D(i) = h; in HELPER()
3136 env->cf[cd & 0x7] = do_match2(0, Vj->D(0), Vj->D(1), MO); \
3139 do_match2(0, Vj->D(2), Vj->D(3), MO); \
3410 temp.D(2 * i) = (imm & 2 ? Vj : Vd)->D((imm & 1) + 2 * i); in HELPER()
3455 temp.D(0) = Vj->D(imm & 0x3); in HELPER()
3456 temp.D(1) = Vj->D((imm >> 2) & 0x3); in HELPER()
3457 temp.D(2) = Vj->D((imm >> 4) & 0x3); in HELPER()
[all …]
H A Dtranslate.c55 offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); in get_vreg64()
61 offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); in set_vreg64()
225 offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); in get_fpr()
232 offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); in set_fpr()
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc5 * D(OPC, NAME, FMT, FAC, I1, I2, P, W, OP, CC, DATA)
140 D(0x8600, BXH, RS_a, Z, 0, a2, 0, 0, bx32, 0, 0)
141 D(0x8700, BXLE, RS_a, Z, 0, a2, 0, 0, bx32, 0, 1)
142 D(0xeb44, BXHG, RSY_a, Z, 0, a2, 0, 0, bx64, 0, 0)
143 D(0xeb45, BXLEG, RSY_a, Z, 0, a2, 0, 0, bx64, 0, 1)
145 D(0x8400, BRXH, RSI, Z, 0, 0, 0, 0, bx32, 0, 0)
146 D(0x8500, BRXLE, RSI, Z, 0, 0, 0, 0, bx32, 0, 1)
147 D(0xec44, BRXHG, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 0)
148 D(0xec45, BRXHLE, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 1)
800 D(0x010c, SAM24, E, Z, 0, 0, 0, 0, sam, 0, 0)
[all …]
/qemu/hw/dma/
H A Detraxfs_dma.c35 #define D(x) macro
263 D(dump_c(c, &ctrl->channels[c].current_c)); in channel_load_c()
280 D(dump_d(c, &ctrl->channels[c].current_d)); in channel_load_d()
290 D(dump_d(c, &ctrl->channels[c].current_d)); in channel_store_c()
346 D(printf("continue %d ok %x\n", c, in channel_continue()
364 D(printf("%s ch=%d cmd=%x\n", in channel_stream_cmd()
379 D(printf("%s %d\n", __func__, c)); in channel_update_irq()
409 D(printf("ch=%d buf=%x after=%x\n", in channel_out_run()
521 D(printf("in dscr end len=%d\n", in channel_in_process()
543 D(printf("channel %d EOL\n", c)); in channel_in_process()
[all …]
/qemu/docs/interop/
H A Ddbus-vmstate.rst2 D-Bus VMState
6 on a QEMU D-Bus bus. (refer to the :doc:`dbus` document for
7 some recommendations on D-Bus usage)
10 ``org.qemu.VMState1`` D-Bus name owners and query their ``Id``. It
18 1Mb. The state must be saved quickly (a fraction of a second). (D-Bus
33 Sphinx 4 is required to build D-Bus documentation.
H A Ddbus-display.rst1 D-Bus display
4 QEMU can export the VM display through D-Bus (when started with ``-display
8 Various specialized D-Bus interfaces are available on different object paths
26 Sphinx 4 is required to build D-Bus documentation.
H A Dlive-block-operations.rst177 [A] <-- [B] <-- [C] <-- [D]
216 [A] <-- [B] <-- [C] <-- [D]
225 [D]
256 [D]
266 [A] <-- [D]
279 [A] <-- [C] <-- [D]
350 [A] <-- [C] <-- [D]
356 [A] <-- [D]
369 [A] <-- [B] <-- [D]
400 [A] <-- [C] <-- [D]
[all …]
H A Ddbus.rst2 D-Bus
21 display), D-Bus is the de facto IPC of choice on Unix systems. The
33 A QEMU D-Bus bus should be private to a single VM. Thus, only
36 D-Bus, the protocol and standard, doesn't have mechanisms to enforce
44 methods implemented using D-Bus are just as critical. Peers need to
100 When implementing new D-Bus interfaces, it is recommended to follow
101 the "D-Bus API Design Guidelines":
/qemu/target/ppc/
H A Dinsn32.decode35 &D rt ra si:int64_t
36 @D ...... rt:5 ra:5 si:s16 &D
291 LBZ 100010 ..... ..... ................ @D
292 LBZU 100011 ..... ..... ................ @D
296 LHZ 101000 ..... ..... ................ @D
297 LHZU 101001 ..... ..... ................ @D
301 LHA 101010 ..... ..... ................ @D
302 LHAU 101011 ..... ..... ................ @D
306 LWZ 100000 ..... ..... ................ @D
307 LWZU 100001 ..... ..... ................ @D
[all …]
/qemu/hw/ppc/
H A Dppc405_uc.c758 int M, D; in ppc405ep_compute_clocks() local
776 PLL_out = VCO_out / D; in ppc405ep_compute_clocks()
792 CPU_clk = PLL_out / D; in ppc405ep_compute_clocks()
795 PLB_clk = CPU_clk / D; in ppc405ep_compute_clocks()
798 OPB_clk = PLB_clk / D; in ppc405ep_compute_clocks()
801 EBC_clk = PLB_clk / D; in ppc405ep_compute_clocks()
804 MAL_clk = PLB_clk / D; in ppc405ep_compute_clocks()
805 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ in ppc405ep_compute_clocks()
807 PCI_clk = PLB_clk / D; in ppc405ep_compute_clocks()
810 UART0_clk = PLL_out / D; in ppc405ep_compute_clocks()
[all …]
/qemu/hw/net/
H A Dxilinx_ethlite.c34 #define D(x) macro
102 D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr * 4, r)); in eth_read()
128 D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n", in eth_write()
134 D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0])); in eth_write()
158 D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n", in eth_write()
197 D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0])); in eth_rx()
201 D(qemu_log("%s %zd rxbase=%x\n", __func__, size, rxbase)); in eth_rx()
203 D(qemu_log("ethlite packet is too big, size=%x\n", size)); in eth_rx()
H A Detraxfs_eth.c35 #define D(x) macro
394 D(printf("%s %x\n", __func__, addr * 4)); in eth_read()
419 D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma, in eth_update_ma()
465 D(printf("%s %x %x\n", __func__, addr, value)); in eth_write()
511 D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh, in eth_match_groupaddr()
528 D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n", in eth_receive()
550 D(printf("%s buf=%p len=%d\n", __func__, buf, len)); in eth_tx_push()
558 D(printf("%s %d\n", __func__, nc->link_down)); in eth_set_link()
/qemu/hw/timer/
H A Detraxfs_timer.c36 #define D(x) macro
140 D(printf ("%s %x\n", __func__, addr)); in timer_read()
175 D(printf ("extern or disabled timer clock?\n")); in update_ctrl()
186 D(printf ("freq_hz=%d div=%d\n", freq_hz, div)); in update_ctrl()
217 D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr)); in timer_update_irq()
266 D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", in timer_watchdog_update()
301 D(printf ("RW_TMR0_CTRL=%x\n", value)); in timer_write()
309 D(printf ("RW_TMR1_CTRL=%x\n", value)); in timer_write()
314 D(printf ("RW_INTR_MASK=%x\n", value)); in timer_write()
H A Dxilinx_timer.c34 #define D(x) macro
123 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n", in timer_read()
132 D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r)); in timer_read()
141 D(fprintf(stderr, "%s timer=%d down=%d\n", __func__, in timer_enable()
166 D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n", in timer_write()
206 D(fprintf(stderr, "%s %d\n", __func__, xt->nr)); in timer_hit()
/qemu/target/cris/
H A Dmmu.c28 #define D(x) x macro
31 #define D(x) do { } while (0) macro
219 D(printf("tlb: kernel protected %x lo=%x pc=%x\n", in cris_mmu_translate_page()
224 D(printf("tlb: write protected %x lo=%x pc=%x\n", in cris_mmu_translate_page()
230 D(printf("tlb: exec protected %x lo=%x pc=%x\n", in cris_mmu_translate_page()
235 D(printf("tlb: invalid %x\n", vaddr)); in cris_mmu_translate_page()
250 D(dump_tlb(env, mmu)); in cris_mmu_translate_page()
273 D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc)); in cris_mmu_translate_page()
276 D(printf("%s access=%u mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x" in cris_mmu_translate_page()
/qemu/hw/char/
H A Detraxfs_ser.c35 #define D(x) macro
116 D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr, r)); in ser_read()
130 D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr, value)); in ser_write()
146 D(qemu_log("fixedup value=%x r_intr=%x\n", in ser_write()
151 D(printf("r_intr=%x\n", s->regs[R_INTR])); in ser_write()
182 D(qemu_log("WARNING: UART dropped char.\n")); in serial_receive()
/qemu/qga/
H A Dmeson.build130 'x86': ['-D', 'Arch=32'],
131 'x86_64': ['-a', 'x64', '-D', 'Arch=64']
144 qemu_ga_msi_vss = ['-D', 'InstallVss']
163 '-D', 'BUILD_DIR=' + meson.project_build_root(),
164 '-D', 'BIN_DIR=' + glib_pc.get_variable('bindir'),
165 '-D', 'QEMU_GA_VERSION=' + qga_msi_version,
166 '-D', 'QEMU_GA_MANUFACTURER=' + get_option('qemu_ga_manufacturer'),
167 '-D', 'QEMU_GA_DISTRO=' + get_option('qemu_ga_distro'),
168 '-D', 'LIBPCRE=' + libpcre,
/qemu/pc-bios/
H A Dqemu.rsrc109 $"DE8C 5644 4244 8043 8245 8344 8245 8644" /* fiåVDBDÄCÇEÉDÇEÜD */
123 $"300D B000 030E 2F28 6099 FE01 9C27 882D" /* 0.∞.../(`ô˛.ú'à- */
124 $"802E 882D 822E 872D 0130 1DB2 0003 1B29" /* Ä.à-Ç.á-.0.≤...) */
134 $"801E 861D 801C 811D 011C 09B9 0000 8C96" /* Ä.Ü.Ä.Å...∆π..åñ */
281 $"8348 8047 0144 0CAA 0001 1C48 8045 0244" /* ÉHÄG.D.™...HÄE.D */
283 $"8344 8245 8644 8145 0147 33AB 0001 0C3F" /* ÉDÇEÜDÅE.G3´...? */
284 $"8041 0140 449D 5204 5352 4942 4082 4185" /* ÄA.@DùR.SRIB@ÇAÖ */
298 $"882D 822E 872D 0130 1DB2 0003 1B2C 3251" /* à-Ç.á-.0.≤...,2Q */
323 $"0002 154C 538D 5202 5348 08E8 0002 184D" /* ...LSçR.SH.Ë...M */
440 $"4382 4583 4482 4586 4481 4501 4733 AB00" /* CÇEÉDÇEÜDÅE.G3´. */
[all …]
/qemu/target/loongarch/
H A Dvec.h15 #define D(x) D[(x) ^ 1] macro
25 #define D(x) D[x] macro
/qemu/hw/cris/
H A Daxis_dev88.c40 #define D(x) macro
102 D(printf("%s clk=%d state=%d sr=%x\n", __func__, in tempsensor_clkedge()
138 D(printf("%s cfgreg=%x\n", __func__, s->shiftreg)); in tempsensor_clkedge()
199 D(printf("%s %x=%x\n", __func__, addr, r)); in gpio_read()
206 D(printf("%s %x=%x\n", __func__, addr, (unsigned)value)); in gpio_write()
/qemu/hw/intc/
H A Detraxfs_pic.c32 #define D(x) macro
90 D(printf("%s %x=%x\n", __func__, addr, rval)); in pic_read()
98 D(printf("%s addr=%x val=%x\n", __func__, addr, value)); in pic_write()
H A Dxilinx_intc.c32 #define D(x) macro
104 D(printf("%s %x=%x\n", __func__, addr * 4, r)); in pic_read()
115 D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value)); in pic_write()
/qemu/docs/system/devices/
H A Dvirtio-gpu.rst26 **Backends:** QEMU provides a 2D virtio-gpu backend, and two accelerated
46 The default 2D backend only performs 2D operations. The guest needs to
47 employ a software renderer for 3D graphics.
100 render target to the Pixman buffer if a virtio-gpu 2D hypercall is issued.
/qemu/tests/tcg/i386/
H A DMakefile.target49 $(<D)/test-i386.c $(<D)/test-i386-code16.S $(<D)/test-i386-vm86.S -lm

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