xref: /qemu/include/hw/intc/loongarch_extioi.h (revision dc6f37eb)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * LoongArch 3A5000 ext interrupt controller definitions
4  *
5  * Copyright (C) 2021 Loongson Technology Corporation Limited
6  */
7 
8 #include "hw/sysbus.h"
9 #include "hw/loongarch/virt.h"
10 
11 #ifndef LOONGARCH_EXTIOI_H
12 #define LOONGARCH_EXTIOI_H
13 
14 #define LS3A_INTC_IP               8
15 #define EXTIOI_IRQS                (256)
16 #define EXTIOI_IRQS_BITMAP_SIZE    (256 / 8)
17 /* irq from EXTIOI is routed to no more than 4 cpus */
18 #define EXTIOI_CPUS                (4)
19 /* map to ipnum per 32 irqs */
20 #define EXTIOI_IRQS_IPMAP_SIZE     (256 / 32)
21 #define EXTIOI_IRQS_COREMAP_SIZE   256
22 #define EXTIOI_IRQS_NODETYPE_COUNT  16
23 #define EXTIOI_IRQS_GROUP_COUNT    8
24 
25 #define APIC_OFFSET                  0x400
26 #define APIC_BASE                    (0x1000ULL + APIC_OFFSET)
27 
28 #define EXTIOI_NODETYPE_START        (0x4a0 - APIC_OFFSET)
29 #define EXTIOI_NODETYPE_END          (0x4c0 - APIC_OFFSET)
30 #define EXTIOI_IPMAP_START           (0x4c0 - APIC_OFFSET)
31 #define EXTIOI_IPMAP_END             (0x4c8 - APIC_OFFSET)
32 #define EXTIOI_ENABLE_START          (0x600 - APIC_OFFSET)
33 #define EXTIOI_ENABLE_END            (0x620 - APIC_OFFSET)
34 #define EXTIOI_BOUNCE_START          (0x680 - APIC_OFFSET)
35 #define EXTIOI_BOUNCE_END            (0x6a0 - APIC_OFFSET)
36 #define EXTIOI_ISR_START             (0x700 - APIC_OFFSET)
37 #define EXTIOI_ISR_END               (0x720 - APIC_OFFSET)
38 #define EXTIOI_COREISR_START         (0x800 - APIC_OFFSET)
39 #define EXTIOI_COREISR_END           (0xB20 - APIC_OFFSET)
40 #define EXTIOI_COREMAP_START         (0xC00 - APIC_OFFSET)
41 #define EXTIOI_COREMAP_END           (0xD00 - APIC_OFFSET)
42 #define EXTIOI_SIZE                  0x800
43 
44 #define EXTIOI_VIRT_BASE             (0x40000000)
45 #define EXTIOI_VIRT_SIZE             (0x1000)
46 #define EXTIOI_VIRT_FEATURES         (0x0)
47 #define  EXTIOI_HAS_VIRT_EXTENSION   (0)
48 #define  EXTIOI_HAS_ENABLE_OPTION    (1)
49 #define  EXTIOI_HAS_INT_ENCODE       (2)
50 #define  EXTIOI_HAS_CPU_ENCODE       (3)
51 #define  EXTIOI_VIRT_HAS_FEATURES    (BIT(EXTIOI_HAS_VIRT_EXTENSION)  \
52                                       | BIT(EXTIOI_HAS_ENABLE_OPTION) \
53                                       | BIT(EXTIOI_HAS_INT_ENCODE)    \
54                                       | BIT(EXTIOI_HAS_CPU_ENCODE))
55 #define EXTIOI_VIRT_CONFIG           (0x4)
56 #define  EXTIOI_ENABLE               (1)
57 #define  EXTIOI_ENABLE_INT_ENCODE    (2)
58 #define  EXTIOI_ENABLE_CPU_ENCODE    (3)
59 #define EXTIOI_VIRT_COREMAP_START    (0x40)
60 #define EXTIOI_VIRT_COREMAP_END      (0x240)
61 
62 typedef struct ExtIOICore {
63     uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
64     DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
65     qemu_irq parent_irq[LS3A_INTC_IP];
66 } ExtIOICore;
67 
68 #define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
69 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
70 struct LoongArchExtIOI {
71     SysBusDevice parent_obj;
72     uint32_t num_cpu;
73     uint32_t features;
74     uint32_t status;
75     /* hardware state */
76     uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
77     uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
78     uint32_t isr[EXTIOI_IRQS / 32];
79     uint32_t enable[EXTIOI_IRQS / 32];
80     uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
81     uint32_t coremap[EXTIOI_IRQS / 4];
82     uint32_t sw_pending[EXTIOI_IRQS / 32];
83     uint8_t  sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
84     uint8_t  sw_coremap[EXTIOI_IRQS];
85     qemu_irq irq[EXTIOI_IRQS];
86     ExtIOICore *cpu;
87     MemoryRegion extioi_system_mem;
88     MemoryRegion virt_extend;
89 };
90 #endif /* LOONGARCH_EXTIOI_H */
91