Searched refs:INT_MASK (Results 1 – 5 of 5) sorted by relevance
/qemu/hw/adc/ |
H A D | zynq-xadc.c | 27 INT_MASK, enumerator 89 qemu_set_irq(s->irq, !!(s->regs[INT_STS] & ~s->regs[INT_MASK])); in zynq_xadc_update_ints() 99 s->regs[INT_MASK] = 0xffffffff; in zynq_xadc_reset() 140 case INT_MASK: in zynq_xadc_check_offset() 168 case INT_MASK: in zynq_xadc_read() 211 case INT_MASK: in zynq_xadc_write() 212 s->regs[INT_MASK] = val & INT_ALL; in zynq_xadc_write()
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/qemu/hw/net/ |
H A D | opencores_eth.c | 139 INT_MASK, enumerator 318 open_eth_update_irq(s, old_val & s->regs[INT_MASK], in open_eth_int_source_write() 319 s->regs[INT_SOURCE] & s->regs[INT_MASK]); in open_eth_int_source_write() 604 open_eth_update_irq(s, old & s->regs[INT_MASK], 605 s->regs[INT_SOURCE] & s->regs[INT_MASK]); 610 uint32_t old = s->regs[INT_MASK]; 612 s->regs[INT_MASK] = val; 614 s->regs[INT_SOURCE] & s->regs[INT_MASK]); 666 [INT_MASK] = open_eth_int_mask_host_write,
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H A D | eepro100.c | 131 #define INT_MASK 0x0100 macro
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/qemu/hw/dma/ |
H A D | xlnx_csu_dma.c | 86 REG32(INT_MASK, 0x20) 87 FIELD(INT_MASK, FIFO_OVERFLOW, 7, 1) /* ro, reset: 0x1 */ 88 FIELD(INT_MASK, INVALID_APB, 6, 1) /* ro, reset: 0x1 */ 89 FIELD(INT_MASK, THRESH_HIT, 5, 1) /* ro, reset: 0x1 */ 90 FIELD(INT_MASK, TIMEOUT_MEM, 4, 1) /* ro, reset: 0x1 */ 91 FIELD(INT_MASK, TIMEOUT_STRM, 3, 1) /* ro, reset: 0x1 */ 92 FIELD(INT_MASK, AXI_BRESP_ERR, 2, 1) /* ro, reset: 0x1, SRC: AXI_RDERR */ 93 FIELD(INT_MASK, DONE, 1, 1) /* ro, reset: 0x1 */ 94 FIELD(INT_MASK, MEM_DONE, 0, 1) /* ro, reset: 0x1 */
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H A D | xlnx-zynq-devcfg.c | 108 REG32(INT_MASK, 0x10)
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