Searched refs:MII_BMCR (Results 1 – 13 of 13) sorted by relevance
25 #define MII_BMCR 0 /* Basic mode control register */ macro
86 s->regs[MII_BMCR] = MII_BMCR_AUTOEN; in mii_reset()106 s->regs[MII_BMCR] = v; in mii_write_bmcr()113 [MII_BMCR] = mii_write_bmcr, in mii_write_host()
65 case MII_BMCR: in RTL8201CP_mdio_read()105 case MII_BMCR: in RTL8201CP_mdio_write()
197 s->phy_regs[MII_BMCR] = 0x1140; in msf2_phy_reset()219 case MII_BMCR: in write_to_phy()
179 return (s->phy_reg[MII_BMCR] & MII_BMCR_AUTOEN); in have_autoneg()186 s->phy_reg[MII_BMCR] = val & ~(0x3f | in set_phy_ctrl()201 [MII_BMCR] = set_phy_ctrl,210 [MII_BMCR] = PHY_RW, [MII_CTRL1000] = PHY_RW,219 [MII_BMCR] = MII_BMCR_SPEED1000 |564 if (s->phy_reg[MII_BMCR] & MII_BMCR_LOOPBACK) { in e1000_send_packet()
118 [MII_BMCR] = MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000,675 case MII_BMCR: in npcm_gmac_mdio_access()
650 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || in e1000e_tx_pkt_send()1740 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; in e1000e_have_autoneg()1765 core->phy[0][MII_BMCR] = val & ~(0x3f | in e1000e_set_phy_ctrl()1945 [MII_BMCR] = e1000e_set_phy_ctrl,2208 [MII_BMCR] = PHY_ANYPAGE | PHY_RW,3367 [MII_BMCR] = MII_BMCR_SPEED1000 |
306 case MII_BMCR: /* Basic Control */ in do_phy_read()371 case MII_BMCR: /* Basic Control */ in do_phy_write()
331 case MII_BMCR: in mcf_fec_read_mdio()
558 if ((core->phy[MII_BMCR] & MII_BMCR_LOOPBACK) || in igb_tx_pkt_send()2110 return core->phy[MII_BMCR] & MII_BMCR_AUTOEN; in igb_have_autoneg()2134 core->phy[MII_BMCR] = val & ~(0x3f | MII_BMCR_RESET | MII_BMCR_ANRESTART); in igb_set_phy_ctrl()2650 [MII_BMCR] = PHY_RW,2676 if (addr == MII_BMCR) { in igb_phy_reg_write()4330 [MII_BMCR] = MII_BMCR_SPEED1000 |
423 case MII_BMCR: in sunhme_mii_write()
773 case MII_BMCR: in __sungem_mii_read()
70 (MII_BMCR << E1000_MDIC_REG_SHIFT) | in igb_pci_start_hw()