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Searched refs:MMCR0_PMCjCE (Results 1 – 3 of 3) sorted by relevance

/qemu/target/ppc/
H A Dpower8-pmu.c31 return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; in pmc_has_overflow_enabled()
157 if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { in pmu_increment_insns()
167 if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { in pmu_increment_insns()
180 if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { in pmu_increment_insns()
191 if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { in pmu_increment_insns()
H A Dhelper_regs.c94 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) { in hreg_compute_pmu_hflags_value()
H A Dcpu.h535 #define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ macro