Searched refs:MSR_PR (Results 1 – 5 of 5) sorted by relevance
53 bool pr = !!(env->msr & (1 << MSR_PR)); in hreg_check_bhrb_enable()138 QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR); in hreg_compute_hflags_value()141 msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | in hreg_compute_hflags_value()219 dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1; in hreg_compute_hflags_value()335 if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { in hreg_store_msr()
2175 (1ull << MSR_PR) |2246 (1ull << MSR_PR) |2285 (1ull << MSR_PR) |2337 (1ull << MSR_PR) |2407 (1ull << MSR_PR) |2446 (1ull << MSR_PR) |2488 (1ull << MSR_PR) | in POWERPC_FAMILY()2530 (1ull << MSR_PR) | in POWERPC_FAMILY()2586 (1ull << MSR_PR) | in POWERPC_FAMILY()2626 (1ull << MSR_PR) | in POWERPC_FAMILY()[all …]
3231 return env->msr & ((target_ulong)1 << MSR_PR); in ppc_cpu_debug_check_breakpoint()3233 return (!(env->msr & ((target_ulong)1 << MSR_PR)) && in ppc_cpu_debug_check_breakpoint()3236 return (!(env->msr & ((target_ulong)1 << MSR_PR)) && in ppc_cpu_debug_check_breakpoint()3261 if ((env->msr & ((target_ulong)1 << MSR_PR)) && !pr) { in ppc_cpu_debug_check_watchpoint()
444 #define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */ macro494 FIELD(MSR, PR, MSR_PR, 1)
70 * check MSR_PR as well.