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Searched refs:MSR_VM (Results 1 – 4 of 4) sorted by relevance

/qemu/target/microblaze/
H A Dcpu.h72 #define MSR_VM (1<<13) /* Virtual Mode */ macro
75 #define MSR_KERNEL MSR_EE|MSR_VM
281 #define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE)
H A Dhelper.c206 t = (msr & (MSR_VM | MSR_UM)) << 1; in mb_cpu_do_interrupt()
207 msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); in mb_cpu_do_interrupt()
H A Dtranslate.c1198 msr_to_set |= (dc->tb_flags & (MSR_UM | MSR_VM)) << 1; in trans_brki()
1200 ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM)); in trans_brki()
1509 tcg_gen_andi_i32(tmp, tmp, MSR_VM | MSR_UM); in do_rti()
1510 tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM)); in do_rti()
1519 tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_BIP)); in do_rtb()
1520 tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); in do_rtb()
1530 tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); in do_rte()
1531 tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_EIP)); in do_rte()
H A Dcpu.c128 if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { in mb_cpu_mmu_index()
206 mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); in mb_cpu_reset_hold()