1 /*
2 * i386 virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef I386_CPU_H
21 #define I386_CPU_H
22
23 #include "sysemu/tcg.h"
24 #include "cpu-qom.h"
25 #include "kvm/hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27 #include "hw/i386/topology.h"
28 #include "qapi/qapi-types-common.h"
29 #include "qemu/cpu-float.h"
30 #include "qemu/timer.h"
31
32 #define XEN_NR_VIRQS 24
33
34 #define KVM_HAVE_MCE_INJECTION 1
35
36 /* support for self modifying code even if the modified instruction is
37 close to the modifying instruction */
38 #define TARGET_HAS_PRECISE_SMC
39
40 #ifdef TARGET_X86_64
41 #define I386_ELF_MACHINE EM_X86_64
42 #define ELF_MACHINE_UNAME "x86_64"
43 #else
44 #define I386_ELF_MACHINE EM_386
45 #define ELF_MACHINE_UNAME "i686"
46 #endif
47
48 enum {
49 R_EAX = 0,
50 R_ECX = 1,
51 R_EDX = 2,
52 R_EBX = 3,
53 R_ESP = 4,
54 R_EBP = 5,
55 R_ESI = 6,
56 R_EDI = 7,
57 R_R8 = 8,
58 R_R9 = 9,
59 R_R10 = 10,
60 R_R11 = 11,
61 R_R12 = 12,
62 R_R13 = 13,
63 R_R14 = 14,
64 R_R15 = 15,
65
66 R_AL = 0,
67 R_CL = 1,
68 R_DL = 2,
69 R_BL = 3,
70 R_AH = 4,
71 R_CH = 5,
72 R_DH = 6,
73 R_BH = 7,
74 };
75
76 typedef enum X86Seg {
77 R_ES = 0,
78 R_CS = 1,
79 R_SS = 2,
80 R_DS = 3,
81 R_FS = 4,
82 R_GS = 5,
83 R_LDTR = 6,
84 R_TR = 7,
85 } X86Seg;
86
87 /* segment descriptor fields */
88 #define DESC_G_SHIFT 23
89 #define DESC_G_MASK (1 << DESC_G_SHIFT)
90 #define DESC_B_SHIFT 22
91 #define DESC_B_MASK (1 << DESC_B_SHIFT)
92 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
93 #define DESC_L_MASK (1 << DESC_L_SHIFT)
94 #define DESC_AVL_SHIFT 20
95 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
96 #define DESC_P_SHIFT 15
97 #define DESC_P_MASK (1 << DESC_P_SHIFT)
98 #define DESC_DPL_SHIFT 13
99 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
100 #define DESC_S_SHIFT 12
101 #define DESC_S_MASK (1 << DESC_S_SHIFT)
102 #define DESC_TYPE_SHIFT 8
103 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
104 #define DESC_A_MASK (1 << 8)
105
106 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
107 #define DESC_C_MASK (1 << 10) /* code: conforming */
108 #define DESC_R_MASK (1 << 9) /* code: readable */
109
110 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
111 #define DESC_W_MASK (1 << 9) /* data: writable */
112
113 #define DESC_TSS_BUSY_MASK (1 << 9)
114
115 /* eflags masks */
116 #define CC_C 0x0001
117 #define CC_P 0x0004
118 #define CC_A 0x0010
119 #define CC_Z 0x0040
120 #define CC_S 0x0080
121 #define CC_O 0x0800
122
123 #define TF_SHIFT 8
124 #define IOPL_SHIFT 12
125 #define VM_SHIFT 17
126
127 #define TF_MASK 0x00000100
128 #define IF_MASK 0x00000200
129 #define DF_MASK 0x00000400
130 #define IOPL_MASK 0x00003000
131 #define NT_MASK 0x00004000
132 #define RF_MASK 0x00010000
133 #define VM_MASK 0x00020000
134 #define AC_MASK 0x00040000
135 #define VIF_MASK 0x00080000
136 #define VIP_MASK 0x00100000
137 #define ID_MASK 0x00200000
138
139 /* hidden flags - used internally by qemu to represent additional cpu
140 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
141 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
142 positions to ease oring with eflags. */
143 /* current cpl */
144 #define HF_CPL_SHIFT 0
145 /* true if hardware interrupts must be disabled for next instruction */
146 #define HF_INHIBIT_IRQ_SHIFT 3
147 /* 16 or 32 segments */
148 #define HF_CS32_SHIFT 4
149 #define HF_SS32_SHIFT 5
150 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
151 #define HF_ADDSEG_SHIFT 6
152 /* copy of CR0.PE (protected mode) */
153 #define HF_PE_SHIFT 7
154 #define HF_TF_SHIFT 8 /* must be same as eflags */
155 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
156 #define HF_EM_SHIFT 10
157 #define HF_TS_SHIFT 11
158 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
159 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
160 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
161 #define HF_RF_SHIFT 16 /* must be same as eflags */
162 #define HF_VM_SHIFT 17 /* must be same as eflags */
163 #define HF_AC_SHIFT 18 /* must be same as eflags */
164 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
165 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
166 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */
167 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
168 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
169 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
170 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
171 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
172 #define HF_UMIP_SHIFT 27 /* CR4.UMIP */
173 #define HF_AVX_EN_SHIFT 28 /* AVX Enabled (CR4+XCR0) */
174
175 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
176 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
177 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
178 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
179 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
180 #define HF_PE_MASK (1 << HF_PE_SHIFT)
181 #define HF_TF_MASK (1 << HF_TF_SHIFT)
182 #define HF_MP_MASK (1 << HF_MP_SHIFT)
183 #define HF_EM_MASK (1 << HF_EM_SHIFT)
184 #define HF_TS_MASK (1 << HF_TS_SHIFT)
185 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
186 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
187 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
188 #define HF_RF_MASK (1 << HF_RF_SHIFT)
189 #define HF_VM_MASK (1 << HF_VM_SHIFT)
190 #define HF_AC_MASK (1 << HF_AC_SHIFT)
191 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
192 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
193 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
194 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
195 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
196 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
197 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
198 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
199 #define HF_UMIP_MASK (1 << HF_UMIP_SHIFT)
200 #define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT)
201
202 /* hflags2 */
203
204 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
205 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
206 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
207 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
208 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
209 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
210 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
211 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
212 #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/
213
214 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
215 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
216 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
217 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
218 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
219 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
220 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
221 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
222 #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT)
223
224 #define CR0_PE_SHIFT 0
225 #define CR0_MP_SHIFT 1
226
227 #define CR0_PE_MASK (1U << 0)
228 #define CR0_MP_MASK (1U << 1)
229 #define CR0_EM_MASK (1U << 2)
230 #define CR0_TS_MASK (1U << 3)
231 #define CR0_ET_MASK (1U << 4)
232 #define CR0_NE_MASK (1U << 5)
233 #define CR0_WP_MASK (1U << 16)
234 #define CR0_AM_MASK (1U << 18)
235 #define CR0_NW_MASK (1U << 29)
236 #define CR0_CD_MASK (1U << 30)
237 #define CR0_PG_MASK (1U << 31)
238
239 #define CR4_VME_MASK (1U << 0)
240 #define CR4_PVI_MASK (1U << 1)
241 #define CR4_TSD_MASK (1U << 2)
242 #define CR4_DE_MASK (1U << 3)
243 #define CR4_PSE_MASK (1U << 4)
244 #define CR4_PAE_MASK (1U << 5)
245 #define CR4_MCE_MASK (1U << 6)
246 #define CR4_PGE_MASK (1U << 7)
247 #define CR4_PCE_MASK (1U << 8)
248 #define CR4_OSFXSR_SHIFT 9
249 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
250 #define CR4_OSXMMEXCPT_MASK (1U << 10)
251 #define CR4_UMIP_MASK (1U << 11)
252 #define CR4_LA57_MASK (1U << 12)
253 #define CR4_VMXE_MASK (1U << 13)
254 #define CR4_SMXE_MASK (1U << 14)
255 #define CR4_FSGSBASE_MASK (1U << 16)
256 #define CR4_PCIDE_MASK (1U << 17)
257 #define CR4_OSXSAVE_MASK (1U << 18)
258 #define CR4_SMEP_MASK (1U << 20)
259 #define CR4_SMAP_MASK (1U << 21)
260 #define CR4_PKE_MASK (1U << 22)
261 #define CR4_PKS_MASK (1U << 24)
262 #define CR4_LAM_SUP_MASK (1U << 28)
263
264 #define CR4_RESERVED_MASK \
265 (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
266 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
267 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
268 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
269 | CR4_LA57_MASK \
270 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
271 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \
272 | CR4_LAM_SUP_MASK))
273
274 #define DR6_BD (1 << 13)
275 #define DR6_BS (1 << 14)
276 #define DR6_BT (1 << 15)
277 #define DR6_FIXED_1 0xffff0ff0
278
279 #define DR7_GD (1 << 13)
280 #define DR7_TYPE_SHIFT 16
281 #define DR7_LEN_SHIFT 18
282 #define DR7_FIXED_1 0x00000400
283 #define DR7_GLOBAL_BP_MASK 0xaa
284 #define DR7_LOCAL_BP_MASK 0x55
285 #define DR7_MAX_BP 4
286 #define DR7_TYPE_BP_INST 0x0
287 #define DR7_TYPE_DATA_WR 0x1
288 #define DR7_TYPE_IO_RW 0x2
289 #define DR7_TYPE_DATA_RW 0x3
290
291 #define DR_RESERVED_MASK 0xffffffff00000000ULL
292
293 #define PG_PRESENT_BIT 0
294 #define PG_RW_BIT 1
295 #define PG_USER_BIT 2
296 #define PG_PWT_BIT 3
297 #define PG_PCD_BIT 4
298 #define PG_ACCESSED_BIT 5
299 #define PG_DIRTY_BIT 6
300 #define PG_PSE_BIT 7
301 #define PG_GLOBAL_BIT 8
302 #define PG_PSE_PAT_BIT 12
303 #define PG_PKRU_BIT 59
304 #define PG_NX_BIT 63
305
306 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
307 #define PG_RW_MASK (1 << PG_RW_BIT)
308 #define PG_USER_MASK (1 << PG_USER_BIT)
309 #define PG_PWT_MASK (1 << PG_PWT_BIT)
310 #define PG_PCD_MASK (1 << PG_PCD_BIT)
311 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
312 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
313 #define PG_PSE_MASK (1 << PG_PSE_BIT)
314 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
315 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
316 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
317 #define PG_HI_USER_MASK 0x7ff0000000000000LL
318 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
319 #define PG_NX_MASK (1ULL << PG_NX_BIT)
320
321 #define PG_ERROR_W_BIT 1
322
323 #define PG_ERROR_P_MASK 0x01
324 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
325 #define PG_ERROR_U_MASK 0x04
326 #define PG_ERROR_RSVD_MASK 0x08
327 #define PG_ERROR_I_D_MASK 0x10
328 #define PG_ERROR_PK_MASK 0x20
329
330 #define PG_MODE_PAE (1 << 0)
331 #define PG_MODE_LMA (1 << 1)
332 #define PG_MODE_NXE (1 << 2)
333 #define PG_MODE_PSE (1 << 3)
334 #define PG_MODE_LA57 (1 << 4)
335 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
336
337 /* Bits of CR4 that do not affect the NPT page format. */
338 #define PG_MODE_WP (1 << 16)
339 #define PG_MODE_PKE (1 << 17)
340 #define PG_MODE_PKS (1 << 18)
341 #define PG_MODE_SMEP (1 << 19)
342
343 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
344 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
345 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
346
347 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
348 #define MCE_BANKS_DEF 10
349
350 #define MCG_CAP_BANKS_MASK 0xff
351
352 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
353 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
354 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
355 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
356
357 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
358
359 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
360 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
361 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
362 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
363 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
364 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
365 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
366 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
367 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
368
369 /* MISC register defines */
370 #define MCM_ADDR_SEGOFF 0 /* segment offset */
371 #define MCM_ADDR_LINEAR 1 /* linear address */
372 #define MCM_ADDR_PHYS 2 /* physical address */
373 #define MCM_ADDR_MEM 3 /* memory address */
374 #define MCM_ADDR_GENERIC 7 /* generic */
375
376 #define MSR_IA32_TSC 0x10
377 #define MSR_IA32_APICBASE 0x1b
378 #define MSR_IA32_APICBASE_BSP (1<<8)
379 #define MSR_IA32_APICBASE_ENABLE (1<<11)
380 #define MSR_IA32_APICBASE_EXTD (1 << 10)
381 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
382 #define MSR_IA32_APICBASE_RESERVED \
383 (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \
384 | MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_BASE))
385
386 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
387 #define MSR_TSC_ADJUST 0x0000003b
388 #define MSR_IA32_SPEC_CTRL 0x48
389 #define MSR_VIRT_SSBD 0xc001011f
390 #define MSR_IA32_PRED_CMD 0x49
391 #define MSR_IA32_UCODE_REV 0x8b
392 #define MSR_IA32_CORE_CAPABILITY 0xcf
393
394 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
395 #define ARCH_CAP_TSX_CTRL_MSR (1<<7)
396
397 #define MSR_IA32_PERF_CAPABILITIES 0x345
398 #define PERF_CAP_LBR_FMT 0x3f
399
400 #define MSR_IA32_TSX_CTRL 0x122
401 #define MSR_IA32_TSCDEADLINE 0x6e0
402 #define MSR_IA32_PKRS 0x6e1
403 #define MSR_ARCH_LBR_CTL 0x000014ce
404 #define MSR_ARCH_LBR_DEPTH 0x000014cf
405 #define MSR_ARCH_LBR_FROM_0 0x00001500
406 #define MSR_ARCH_LBR_TO_0 0x00001600
407 #define MSR_ARCH_LBR_INFO_0 0x00001200
408
409 #define FEATURE_CONTROL_LOCKED (1<<0)
410 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1)
411 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
412 #define FEATURE_CONTROL_SGX_LC (1ULL << 17)
413 #define FEATURE_CONTROL_SGX (1ULL << 18)
414 #define FEATURE_CONTROL_LMCE (1<<20)
415
416 #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c
417 #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d
418 #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e
419 #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f
420
421 #define MSR_P6_PERFCTR0 0xc1
422
423 #define MSR_IA32_SMBASE 0x9e
424 #define MSR_SMI_COUNT 0x34
425 #define MSR_CORE_THREAD_COUNT 0x35
426 #define MSR_MTRRcap 0xfe
427 #define MSR_MTRRcap_VCNT 8
428 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
429 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
430
431 #define MSR_IA32_SYSENTER_CS 0x174
432 #define MSR_IA32_SYSENTER_ESP 0x175
433 #define MSR_IA32_SYSENTER_EIP 0x176
434
435 #define MSR_MCG_CAP 0x179
436 #define MSR_MCG_STATUS 0x17a
437 #define MSR_MCG_CTL 0x17b
438 #define MSR_MCG_EXT_CTL 0x4d0
439
440 #define MSR_P6_EVNTSEL0 0x186
441
442 #define MSR_IA32_PERF_STATUS 0x198
443
444 #define MSR_IA32_MISC_ENABLE 0x1a0
445 /* Indicates good rep/movs microcode on some processors: */
446 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
447 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
448
449 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
450 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
451
452 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
453
454 #define MSR_MTRRfix64K_00000 0x250
455 #define MSR_MTRRfix16K_80000 0x258
456 #define MSR_MTRRfix16K_A0000 0x259
457 #define MSR_MTRRfix4K_C0000 0x268
458 #define MSR_MTRRfix4K_C8000 0x269
459 #define MSR_MTRRfix4K_D0000 0x26a
460 #define MSR_MTRRfix4K_D8000 0x26b
461 #define MSR_MTRRfix4K_E0000 0x26c
462 #define MSR_MTRRfix4K_E8000 0x26d
463 #define MSR_MTRRfix4K_F0000 0x26e
464 #define MSR_MTRRfix4K_F8000 0x26f
465
466 #define MSR_PAT 0x277
467
468 #define MSR_MTRRdefType 0x2ff
469
470 #define MSR_CORE_PERF_FIXED_CTR0 0x309
471 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
472 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
473 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
474 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
475 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
476 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
477
478 #define MSR_MC0_CTL 0x400
479 #define MSR_MC0_STATUS 0x401
480 #define MSR_MC0_ADDR 0x402
481 #define MSR_MC0_MISC 0x403
482
483 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
484 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
485 #define MSR_IA32_RTIT_CTL 0x570
486 #define MSR_IA32_RTIT_STATUS 0x571
487 #define MSR_IA32_RTIT_CR3_MATCH 0x572
488 #define MSR_IA32_RTIT_ADDR0_A 0x580
489 #define MSR_IA32_RTIT_ADDR0_B 0x581
490 #define MSR_IA32_RTIT_ADDR1_A 0x582
491 #define MSR_IA32_RTIT_ADDR1_B 0x583
492 #define MSR_IA32_RTIT_ADDR2_A 0x584
493 #define MSR_IA32_RTIT_ADDR2_B 0x585
494 #define MSR_IA32_RTIT_ADDR3_A 0x586
495 #define MSR_IA32_RTIT_ADDR3_B 0x587
496 #define MAX_RTIT_ADDRS 8
497
498 #define MSR_EFER 0xc0000080
499
500 #define MSR_EFER_SCE (1 << 0)
501 #define MSR_EFER_LME (1 << 8)
502 #define MSR_EFER_LMA (1 << 10)
503 #define MSR_EFER_NXE (1 << 11)
504 #define MSR_EFER_SVME (1 << 12)
505 #define MSR_EFER_FFXSR (1 << 14)
506
507 #define MSR_EFER_RESERVED\
508 (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
509 | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
510 | MSR_EFER_FFXSR))
511
512 #define MSR_STAR 0xc0000081
513 #define MSR_LSTAR 0xc0000082
514 #define MSR_CSTAR 0xc0000083
515 #define MSR_FMASK 0xc0000084
516 #define MSR_FSBASE 0xc0000100
517 #define MSR_GSBASE 0xc0000101
518 #define MSR_KERNELGSBASE 0xc0000102
519 #define MSR_TSC_AUX 0xc0000103
520 #define MSR_AMD64_TSC_RATIO 0xc0000104
521
522 #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
523
524 #define MSR_VM_HSAVE_PA 0xc0010117
525
526 #define MSR_IA32_XFD 0x000001c4
527 #define MSR_IA32_XFD_ERR 0x000001c5
528
529 #define MSR_IA32_BNDCFGS 0x00000d90
530 #define MSR_IA32_XSS 0x00000da0
531 #define MSR_IA32_UMWAIT_CONTROL 0xe1
532
533 #define MSR_IA32_VMX_BASIC 0x00000480
534 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
535 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
536 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
537 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
538 #define MSR_IA32_VMX_MISC 0x00000485
539 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
540 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
541 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
542 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
543 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
544 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
545 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
546 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
547 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
548 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
549 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
550 #define MSR_IA32_VMX_VMFUNC 0x00000491
551
552 #define MSR_APIC_START 0x00000800
553 #define MSR_APIC_END 0x000008ff
554
555 #define XSTATE_FP_BIT 0
556 #define XSTATE_SSE_BIT 1
557 #define XSTATE_YMM_BIT 2
558 #define XSTATE_BNDREGS_BIT 3
559 #define XSTATE_BNDCSR_BIT 4
560 #define XSTATE_OPMASK_BIT 5
561 #define XSTATE_ZMM_Hi256_BIT 6
562 #define XSTATE_Hi16_ZMM_BIT 7
563 #define XSTATE_PKRU_BIT 9
564 #define XSTATE_ARCH_LBR_BIT 15
565 #define XSTATE_XTILE_CFG_BIT 17
566 #define XSTATE_XTILE_DATA_BIT 18
567
568 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
569 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
570 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
571 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
572 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
573 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
574 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
575 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
576 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
577 #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
578 #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
579 #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT)
580
581 #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK)
582
583 #define ESA_FEATURE_ALIGN64_BIT 1
584 #define ESA_FEATURE_XFD_BIT 2
585
586 #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
587 #define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT)
588
589
590 /* CPUID feature bits available in XCR0 */
591 #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
592 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
593 XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
594 XSTATE_ZMM_Hi256_MASK | \
595 XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
596 XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
597
598 /* CPUID feature words */
599 typedef enum FeatureWord {
600 FEAT_1_EDX, /* CPUID[1].EDX */
601 FEAT_1_ECX, /* CPUID[1].ECX */
602 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
603 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
604 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
605 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */
606 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
607 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
608 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
609 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
610 FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
611 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
612 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
613 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */
614 FEAT_SVM, /* CPUID[8000_000A].EDX */
615 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
616 FEAT_6_EAX, /* CPUID[6].EAX */
617 FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
618 FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
619 FEAT_ARCH_CAPABILITIES,
620 FEAT_CORE_CAPABILITY,
621 FEAT_PERF_CAPABILITIES,
622 FEAT_VMX_PROCBASED_CTLS,
623 FEAT_VMX_SECONDARY_CTLS,
624 FEAT_VMX_PINBASED_CTLS,
625 FEAT_VMX_EXIT_CTLS,
626 FEAT_VMX_ENTRY_CTLS,
627 FEAT_VMX_MISC,
628 FEAT_VMX_EPT_VPID_CAPS,
629 FEAT_VMX_BASIC,
630 FEAT_VMX_VMFUNC,
631 FEAT_14_0_ECX,
632 FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
633 FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
634 FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
635 FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */
636 FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */
637 FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */
638 FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */
639 FEATURE_WORDS,
640 } FeatureWord;
641
642 typedef uint64_t FeatureWordArray[FEATURE_WORDS];
643 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
644 bool migratable_only);
645
646 /* cpuid_features bits */
647 #define CPUID_FP87 (1U << 0)
648 #define CPUID_VME (1U << 1)
649 #define CPUID_DE (1U << 2)
650 #define CPUID_PSE (1U << 3)
651 #define CPUID_TSC (1U << 4)
652 #define CPUID_MSR (1U << 5)
653 #define CPUID_PAE (1U << 6)
654 #define CPUID_MCE (1U << 7)
655 #define CPUID_CX8 (1U << 8)
656 #define CPUID_APIC (1U << 9)
657 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
658 #define CPUID_MTRR (1U << 12)
659 #define CPUID_PGE (1U << 13)
660 #define CPUID_MCA (1U << 14)
661 #define CPUID_CMOV (1U << 15)
662 #define CPUID_PAT (1U << 16)
663 #define CPUID_PSE36 (1U << 17)
664 #define CPUID_PN (1U << 18)
665 #define CPUID_CLFLUSH (1U << 19)
666 #define CPUID_DTS (1U << 21)
667 #define CPUID_ACPI (1U << 22)
668 #define CPUID_MMX (1U << 23)
669 #define CPUID_FXSR (1U << 24)
670 #define CPUID_SSE (1U << 25)
671 #define CPUID_SSE2 (1U << 26)
672 #define CPUID_SS (1U << 27)
673 #define CPUID_HT (1U << 28)
674 #define CPUID_TM (1U << 29)
675 #define CPUID_IA64 (1U << 30)
676 #define CPUID_PBE (1U << 31)
677
678 #define CPUID_EXT_SSE3 (1U << 0)
679 #define CPUID_EXT_PCLMULQDQ (1U << 1)
680 #define CPUID_EXT_DTES64 (1U << 2)
681 #define CPUID_EXT_MONITOR (1U << 3)
682 #define CPUID_EXT_DSCPL (1U << 4)
683 #define CPUID_EXT_VMX (1U << 5)
684 #define CPUID_EXT_SMX (1U << 6)
685 #define CPUID_EXT_EST (1U << 7)
686 #define CPUID_EXT_TM2 (1U << 8)
687 #define CPUID_EXT_SSSE3 (1U << 9)
688 #define CPUID_EXT_CID (1U << 10)
689 #define CPUID_EXT_FMA (1U << 12)
690 #define CPUID_EXT_CX16 (1U << 13)
691 #define CPUID_EXT_XTPR (1U << 14)
692 #define CPUID_EXT_PDCM (1U << 15)
693 #define CPUID_EXT_PCID (1U << 17)
694 #define CPUID_EXT_DCA (1U << 18)
695 #define CPUID_EXT_SSE41 (1U << 19)
696 #define CPUID_EXT_SSE42 (1U << 20)
697 #define CPUID_EXT_X2APIC (1U << 21)
698 #define CPUID_EXT_MOVBE (1U << 22)
699 #define CPUID_EXT_POPCNT (1U << 23)
700 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
701 #define CPUID_EXT_AES (1U << 25)
702 #define CPUID_EXT_XSAVE (1U << 26)
703 #define CPUID_EXT_OSXSAVE (1U << 27)
704 #define CPUID_EXT_AVX (1U << 28)
705 #define CPUID_EXT_F16C (1U << 29)
706 #define CPUID_EXT_RDRAND (1U << 30)
707 #define CPUID_EXT_HYPERVISOR (1U << 31)
708
709 #define CPUID_EXT2_FPU (1U << 0)
710 #define CPUID_EXT2_VME (1U << 1)
711 #define CPUID_EXT2_DE (1U << 2)
712 #define CPUID_EXT2_PSE (1U << 3)
713 #define CPUID_EXT2_TSC (1U << 4)
714 #define CPUID_EXT2_MSR (1U << 5)
715 #define CPUID_EXT2_PAE (1U << 6)
716 #define CPUID_EXT2_MCE (1U << 7)
717 #define CPUID_EXT2_CX8 (1U << 8)
718 #define CPUID_EXT2_APIC (1U << 9)
719 #define CPUID_EXT2_SYSCALL (1U << 11)
720 #define CPUID_EXT2_MTRR (1U << 12)
721 #define CPUID_EXT2_PGE (1U << 13)
722 #define CPUID_EXT2_MCA (1U << 14)
723 #define CPUID_EXT2_CMOV (1U << 15)
724 #define CPUID_EXT2_PAT (1U << 16)
725 #define CPUID_EXT2_PSE36 (1U << 17)
726 #define CPUID_EXT2_MP (1U << 19)
727 #define CPUID_EXT2_NX (1U << 20)
728 #define CPUID_EXT2_MMXEXT (1U << 22)
729 #define CPUID_EXT2_MMX (1U << 23)
730 #define CPUID_EXT2_FXSR (1U << 24)
731 #define CPUID_EXT2_FFXSR (1U << 25)
732 #define CPUID_EXT2_PDPE1GB (1U << 26)
733 #define CPUID_EXT2_RDTSCP (1U << 27)
734 #define CPUID_EXT2_LM (1U << 29)
735 #define CPUID_EXT2_3DNOWEXT (1U << 30)
736 #define CPUID_EXT2_3DNOW (1U << 31)
737
738 /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */
739 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
740 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
741 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
742 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
743 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
744 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
745 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
746 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
747 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
748
749 #define CPUID_EXT3_LAHF_LM (1U << 0)
750 #define CPUID_EXT3_CMP_LEG (1U << 1)
751 #define CPUID_EXT3_SVM (1U << 2)
752 #define CPUID_EXT3_EXTAPIC (1U << 3)
753 #define CPUID_EXT3_CR8LEG (1U << 4)
754 #define CPUID_EXT3_ABM (1U << 5)
755 #define CPUID_EXT3_SSE4A (1U << 6)
756 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
757 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
758 #define CPUID_EXT3_OSVW (1U << 9)
759 #define CPUID_EXT3_IBS (1U << 10)
760 #define CPUID_EXT3_XOP (1U << 11)
761 #define CPUID_EXT3_SKINIT (1U << 12)
762 #define CPUID_EXT3_WDT (1U << 13)
763 #define CPUID_EXT3_LWP (1U << 15)
764 #define CPUID_EXT3_FMA4 (1U << 16)
765 #define CPUID_EXT3_TCE (1U << 17)
766 #define CPUID_EXT3_NODEID (1U << 19)
767 #define CPUID_EXT3_TBM (1U << 21)
768 #define CPUID_EXT3_TOPOEXT (1U << 22)
769 #define CPUID_EXT3_PERFCORE (1U << 23)
770 #define CPUID_EXT3_PERFNB (1U << 24)
771
772 #define CPUID_SVM_NPT (1U << 0)
773 #define CPUID_SVM_LBRV (1U << 1)
774 #define CPUID_SVM_SVMLOCK (1U << 2)
775 #define CPUID_SVM_NRIPSAVE (1U << 3)
776 #define CPUID_SVM_TSCSCALE (1U << 4)
777 #define CPUID_SVM_VMCBCLEAN (1U << 5)
778 #define CPUID_SVM_FLUSHASID (1U << 6)
779 #define CPUID_SVM_DECODEASSIST (1U << 7)
780 #define CPUID_SVM_PAUSEFILTER (1U << 10)
781 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
782 #define CPUID_SVM_AVIC (1U << 13)
783 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
784 #define CPUID_SVM_VGIF (1U << 16)
785 #define CPUID_SVM_VNMI (1U << 25)
786 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
787
788 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
789 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
790 /* Support SGX */
791 #define CPUID_7_0_EBX_SGX (1U << 2)
792 /* 1st Group of Advanced Bit Manipulation Extensions */
793 #define CPUID_7_0_EBX_BMI1 (1U << 3)
794 /* Hardware Lock Elision */
795 #define CPUID_7_0_EBX_HLE (1U << 4)
796 /* Intel Advanced Vector Extensions 2 */
797 #define CPUID_7_0_EBX_AVX2 (1U << 5)
798 /* Supervisor-mode Execution Prevention */
799 #define CPUID_7_0_EBX_SMEP (1U << 7)
800 /* 2nd Group of Advanced Bit Manipulation Extensions */
801 #define CPUID_7_0_EBX_BMI2 (1U << 8)
802 /* Enhanced REP MOVSB/STOSB */
803 #define CPUID_7_0_EBX_ERMS (1U << 9)
804 /* Invalidate Process-Context Identifier */
805 #define CPUID_7_0_EBX_INVPCID (1U << 10)
806 /* Restricted Transactional Memory */
807 #define CPUID_7_0_EBX_RTM (1U << 11)
808 /* Memory Protection Extension */
809 #define CPUID_7_0_EBX_MPX (1U << 14)
810 /* AVX-512 Foundation */
811 #define CPUID_7_0_EBX_AVX512F (1U << 16)
812 /* AVX-512 Doubleword & Quadword Instruction */
813 #define CPUID_7_0_EBX_AVX512DQ (1U << 17)
814 /* Read Random SEED */
815 #define CPUID_7_0_EBX_RDSEED (1U << 18)
816 /* ADCX and ADOX instructions */
817 #define CPUID_7_0_EBX_ADX (1U << 19)
818 /* Supervisor Mode Access Prevention */
819 #define CPUID_7_0_EBX_SMAP (1U << 20)
820 /* AVX-512 Integer Fused Multiply Add */
821 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
822 /* Flush a Cache Line Optimized */
823 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
824 /* Cache Line Write Back */
825 #define CPUID_7_0_EBX_CLWB (1U << 24)
826 /* Intel Processor Trace */
827 #define CPUID_7_0_EBX_INTEL_PT (1U << 25)
828 /* AVX-512 Prefetch */
829 #define CPUID_7_0_EBX_AVX512PF (1U << 26)
830 /* AVX-512 Exponential and Reciprocal */
831 #define CPUID_7_0_EBX_AVX512ER (1U << 27)
832 /* AVX-512 Conflict Detection */
833 #define CPUID_7_0_EBX_AVX512CD (1U << 28)
834 /* SHA1/SHA256 Instruction Extensions */
835 #define CPUID_7_0_EBX_SHA_NI (1U << 29)
836 /* AVX-512 Byte and Word Instructions */
837 #define CPUID_7_0_EBX_AVX512BW (1U << 30)
838 /* AVX-512 Vector Length Extensions */
839 #define CPUID_7_0_EBX_AVX512VL (1U << 31)
840
841 /* AVX-512 Vector Byte Manipulation Instruction */
842 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
843 /* User-Mode Instruction Prevention */
844 #define CPUID_7_0_ECX_UMIP (1U << 2)
845 /* Protection Keys for User-mode Pages */
846 #define CPUID_7_0_ECX_PKU (1U << 3)
847 /* OS Enable Protection Keys */
848 #define CPUID_7_0_ECX_OSPKE (1U << 4)
849 /* UMONITOR/UMWAIT/TPAUSE Instructions */
850 #define CPUID_7_0_ECX_WAITPKG (1U << 5)
851 /* Additional AVX-512 Vector Byte Manipulation Instruction */
852 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
853 /* Galois Field New Instructions */
854 #define CPUID_7_0_ECX_GFNI (1U << 8)
855 /* Vector AES Instructions */
856 #define CPUID_7_0_ECX_VAES (1U << 9)
857 /* Carry-Less Multiplication Quadword */
858 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
859 /* Vector Neural Network Instructions */
860 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
861 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
862 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
863 /* POPCNT for vectors of DW/QW */
864 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
865 /* 5-level Page Tables */
866 #define CPUID_7_0_ECX_LA57 (1U << 16)
867 /* Read Processor ID */
868 #define CPUID_7_0_ECX_RDPID (1U << 22)
869 /* Bus Lock Debug Exception */
870 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24)
871 /* Cache Line Demote Instruction */
872 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
873 /* Move Doubleword as Direct Store Instruction */
874 #define CPUID_7_0_ECX_MOVDIRI (1U << 27)
875 /* Move 64 Bytes as Direct Store Instruction */
876 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
877 /* Support SGX Launch Control */
878 #define CPUID_7_0_ECX_SGX_LC (1U << 30)
879 /* Protection Keys for Supervisor-mode Pages */
880 #define CPUID_7_0_ECX_PKS (1U << 31)
881
882 /* AVX512 Neural Network Instructions */
883 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
884 /* AVX512 Multiply Accumulation Single Precision */
885 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
886 /* Fast Short Rep Mov */
887 #define CPUID_7_0_EDX_FSRM (1U << 4)
888 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
889 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
890 /* SERIALIZE instruction */
891 #define CPUID_7_0_EDX_SERIALIZE (1U << 14)
892 /* TSX Suspend Load Address Tracking instruction */
893 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
894 /* Architectural LBRs */
895 #define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
896 /* AMX_BF16 instruction */
897 #define CPUID_7_0_EDX_AMX_BF16 (1U << 22)
898 /* AVX512_FP16 instruction */
899 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
900 /* AMX tile (two-dimensional register) */
901 #define CPUID_7_0_EDX_AMX_TILE (1U << 24)
902 /* AMX_INT8 instruction */
903 #define CPUID_7_0_EDX_AMX_INT8 (1U << 25)
904 /* Speculation Control */
905 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
906 /* Single Thread Indirect Branch Predictors */
907 #define CPUID_7_0_EDX_STIBP (1U << 27)
908 /* Flush L1D cache */
909 #define CPUID_7_0_EDX_FLUSH_L1D (1U << 28)
910 /* Arch Capabilities */
911 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
912 /* Core Capability */
913 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
914 /* Speculative Store Bypass Disable */
915 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
916
917 /* AVX VNNI Instruction */
918 #define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
919 /* AVX512 BFloat16 Instruction */
920 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
921 /* CMPCCXADD Instructions */
922 #define CPUID_7_1_EAX_CMPCCXADD (1U << 7)
923 /* Fast Zero REP MOVS */
924 #define CPUID_7_1_EAX_FZRM (1U << 10)
925 /* Fast Short REP STOS */
926 #define CPUID_7_1_EAX_FSRS (1U << 11)
927 /* Fast Short REP CMPS/SCAS */
928 #define CPUID_7_1_EAX_FSRC (1U << 12)
929 /* Support Tile Computational Operations on FP16 Numbers */
930 #define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
931 /* Support for VPMADD52[H,L]UQ */
932 #define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
933 /* Linear Address Masking */
934 #define CPUID_7_1_EAX_LAM (1U << 26)
935
936 /* Support for VPDPB[SU,UU,SS]D[,S] */
937 #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)
938 /* AVX NE CONVERT Instructions */
939 #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5)
940 /* AMX COMPLEX Instructions */
941 #define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8)
942 /* PREFETCHIT0/1 Instructions */
943 #define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
944
945 /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
946 #define CPUID_7_2_EDX_MCDT_NO (1U << 5)
947
948 /* XFD Extend Feature Disabled */
949 #define CPUID_D_1_EAX_XFD (1U << 4)
950
951 /* Packets which contain IP payload have LIP values */
952 #define CPUID_14_0_ECX_LIP (1U << 31)
953
954 /* CLZERO instruction */
955 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
956 /* Always save/restore FP error pointers */
957 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
958 /* Write back and do not invalidate cache */
959 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
960 /* Indirect Branch Prediction Barrier */
961 #define CPUID_8000_0008_EBX_IBPB (1U << 12)
962 /* Indirect Branch Restricted Speculation */
963 #define CPUID_8000_0008_EBX_IBRS (1U << 14)
964 /* Single Thread Indirect Branch Predictors */
965 #define CPUID_8000_0008_EBX_STIBP (1U << 15)
966 /* STIBP mode has enhanced performance and may be left always on */
967 #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17)
968 /* Speculative Store Bypass Disable */
969 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
970 /* Predictive Store Forwarding Disable */
971 #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28)
972
973 /* Processor ignores nested data breakpoints */
974 #define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0)
975 /* LFENCE is always serializing */
976 #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
977 /* Null Selector Clears Base */
978 #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
979 /* Automatic IBRS */
980 #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8)
981
982 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
983 #define CPUID_XSAVE_XSAVEC (1U << 1)
984 #define CPUID_XSAVE_XGETBV1 (1U << 2)
985 #define CPUID_XSAVE_XSAVES (1U << 3)
986
987 #define CPUID_6_EAX_ARAT (1U << 2)
988
989 /* CPUID[0x80000007].EDX flags: */
990 #define CPUID_APM_INVTSC (1U << 8)
991
992 #define CPUID_VENDOR_SZ 12
993
994 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
995 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
996 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
997 #define CPUID_VENDOR_INTEL "GenuineIntel"
998
999 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
1000 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
1001 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
1002 #define CPUID_VENDOR_AMD "AuthenticAMD"
1003
1004 #define CPUID_VENDOR_VIA "CentaurHauls"
1005
1006 #define CPUID_VENDOR_HYGON "HygonGenuine"
1007
1008 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
1009 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
1010 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
1011 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
1012 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
1013 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
1014
1015 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
1016 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
1017
1018 /* CPUID[0xB].ECX level types */
1019 #define CPUID_B_ECX_TOPO_LEVEL_INVALID 0
1020 #define CPUID_B_ECX_TOPO_LEVEL_SMT 1
1021 #define CPUID_B_ECX_TOPO_LEVEL_CORE 2
1022
1023 /* COUID[0x1F].ECX level types */
1024 #define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID
1025 #define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT
1026 #define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE
1027 #define CPUID_1F_ECX_TOPO_LEVEL_MODULE 3
1028 #define CPUID_1F_ECX_TOPO_LEVEL_DIE 5
1029
1030 /* MSR Feature Bits */
1031 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
1032 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
1033 #define MSR_ARCH_CAP_RSBA (1U << 2)
1034 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
1035 #define MSR_ARCH_CAP_SSB_NO (1U << 4)
1036 #define MSR_ARCH_CAP_MDS_NO (1U << 5)
1037 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
1038 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
1039 #define MSR_ARCH_CAP_TAA_NO (1U << 8)
1040 #define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13)
1041 #define MSR_ARCH_CAP_FBSDP_NO (1U << 14)
1042 #define MSR_ARCH_CAP_PSDP_NO (1U << 15)
1043 #define MSR_ARCH_CAP_FB_CLEAR (1U << 17)
1044 #define MSR_ARCH_CAP_PBRSB_NO (1U << 24)
1045
1046 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
1047
1048 /* VMX MSR features */
1049 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
1050 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
1051 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
1052 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
1053 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
1054 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
1055 #define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56)
1056
1057 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
1058 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
1059 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
1060 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
1061 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
1062 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
1063 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
1064 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
1065
1066 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
1067 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
1068 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
1069 #define MSR_VMX_EPT_UC (1ULL << 8)
1070 #define MSR_VMX_EPT_WB (1ULL << 14)
1071 #define MSR_VMX_EPT_2MB (1ULL << 16)
1072 #define MSR_VMX_EPT_1GB (1ULL << 17)
1073 #define MSR_VMX_EPT_INVEPT (1ULL << 20)
1074 #define MSR_VMX_EPT_AD_BITS (1ULL << 21)
1075 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
1076 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
1077 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
1078 #define MSR_VMX_EPT_INVVPID (1ULL << 32)
1079 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
1080 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
1081 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
1082 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1083
1084 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
1085
1086
1087 /* VMX controls */
1088 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
1089 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
1090 #define VMX_CPU_BASED_HLT_EXITING 0x00000080
1091 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
1092 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
1093 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
1094 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
1095 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
1096 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
1097 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
1098 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
1099 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000
1100 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
1101 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
1102 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
1103 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
1104 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
1105 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
1106 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
1107 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
1108 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1109
1110 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1111 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
1112 #define VMX_SECONDARY_EXEC_DESC 0x00000004
1113 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
1114 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
1115 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
1116 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
1117 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
1118 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
1119 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
1120 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
1121 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
1122 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
1123 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
1124 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
1125 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
1126 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
1127 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
1128 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000
1129 #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000
1130 #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE 0x04000000
1131
1132 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
1133 #define VMX_PIN_BASED_NMI_EXITING 0x00000008
1134 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
1135 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
1136 #define VMX_PIN_BASED_POSTED_INTR 0x00000080
1137
1138 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
1139 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
1140 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
1141 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
1142 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
1143 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
1144 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
1145 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
1146 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
1147 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
1148 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
1149 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
1150 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
1151
1152 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
1153 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200
1154 #define VMX_VM_ENTRY_SMM 0x00000400
1155 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
1156 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
1157 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
1158 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
1159 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
1160 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
1161 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
1162 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
1163
1164 /* Supported Hyper-V Enlightenments */
1165 #define HYPERV_FEAT_RELAXED 0
1166 #define HYPERV_FEAT_VAPIC 1
1167 #define HYPERV_FEAT_TIME 2
1168 #define HYPERV_FEAT_CRASH 3
1169 #define HYPERV_FEAT_RESET 4
1170 #define HYPERV_FEAT_VPINDEX 5
1171 #define HYPERV_FEAT_RUNTIME 6
1172 #define HYPERV_FEAT_SYNIC 7
1173 #define HYPERV_FEAT_STIMER 8
1174 #define HYPERV_FEAT_FREQUENCIES 9
1175 #define HYPERV_FEAT_REENLIGHTENMENT 10
1176 #define HYPERV_FEAT_TLBFLUSH 11
1177 #define HYPERV_FEAT_EVMCS 12
1178 #define HYPERV_FEAT_IPI 13
1179 #define HYPERV_FEAT_STIMER_DIRECT 14
1180 #define HYPERV_FEAT_AVIC 15
1181 #define HYPERV_FEAT_SYNDBG 16
1182 #define HYPERV_FEAT_MSR_BITMAP 17
1183 #define HYPERV_FEAT_XMM_INPUT 18
1184 #define HYPERV_FEAT_TLBFLUSH_EXT 19
1185 #define HYPERV_FEAT_TLBFLUSH_DIRECT 20
1186
1187 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1188 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1189 #endif
1190
1191 #define EXCP00_DIVZ 0
1192 #define EXCP01_DB 1
1193 #define EXCP02_NMI 2
1194 #define EXCP03_INT3 3
1195 #define EXCP04_INTO 4
1196 #define EXCP05_BOUND 5
1197 #define EXCP06_ILLOP 6
1198 #define EXCP07_PREX 7
1199 #define EXCP08_DBLE 8
1200 #define EXCP09_XERR 9
1201 #define EXCP0A_TSS 10
1202 #define EXCP0B_NOSEG 11
1203 #define EXCP0C_STACK 12
1204 #define EXCP0D_GPF 13
1205 #define EXCP0E_PAGE 14
1206 #define EXCP10_COPR 16
1207 #define EXCP11_ALGN 17
1208 #define EXCP12_MCHK 18
1209
1210 #define EXCP_VMEXIT 0x100 /* only for system emulation */
1211 #define EXCP_SYSCALL 0x101 /* only for user emulation */
1212 #define EXCP_VSYSCALL 0x102 /* only for user emulation */
1213
1214 /* i386-specific interrupt pending bits. */
1215 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1216 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1217 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1218 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1219 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1220 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1221 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1222
1223 /* Use a clearer name for this. */
1224 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1225
1226 /* Instead of computing the condition codes after each x86 instruction,
1227 * QEMU just stores one operand (called CC_SRC), the result
1228 * (called CC_DST) and the type of operation (called CC_OP). When the
1229 * condition codes are needed, the condition codes can be calculated
1230 * using this information. Condition codes are not generated if they
1231 * are only needed for conditional branches.
1232 */
1233 typedef enum {
1234 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
1235 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
1236
1237 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
1238 CC_OP_MULW,
1239 CC_OP_MULL,
1240 CC_OP_MULQ,
1241
1242 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1243 CC_OP_ADDW,
1244 CC_OP_ADDL,
1245 CC_OP_ADDQ,
1246
1247 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1248 CC_OP_ADCW,
1249 CC_OP_ADCL,
1250 CC_OP_ADCQ,
1251
1252 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1253 CC_OP_SUBW,
1254 CC_OP_SUBL,
1255 CC_OP_SUBQ,
1256
1257 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1258 CC_OP_SBBW,
1259 CC_OP_SBBL,
1260 CC_OP_SBBQ,
1261
1262 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
1263 CC_OP_LOGICW,
1264 CC_OP_LOGICL,
1265 CC_OP_LOGICQ,
1266
1267 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1268 CC_OP_INCW,
1269 CC_OP_INCL,
1270 CC_OP_INCQ,
1271
1272 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1273 CC_OP_DECW,
1274 CC_OP_DECL,
1275 CC_OP_DECQ,
1276
1277 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1278 CC_OP_SHLW,
1279 CC_OP_SHLL,
1280 CC_OP_SHLQ,
1281
1282 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1283 CC_OP_SARW,
1284 CC_OP_SARL,
1285 CC_OP_SARQ,
1286
1287 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1288 CC_OP_BMILGW,
1289 CC_OP_BMILGL,
1290 CC_OP_BMILGQ,
1291
1292 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
1293 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */
1294 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
1295
1296 CC_OP_CLR, /* Z set, all other flags clear. */
1297 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */
1298
1299 CC_OP_NB,
1300 } CCOp;
1301 QEMU_BUILD_BUG_ON(CC_OP_NB >= 128);
1302
1303 typedef struct SegmentCache {
1304 uint32_t selector;
1305 target_ulong base;
1306 uint32_t limit;
1307 uint32_t flags;
1308 } SegmentCache;
1309
1310 typedef union MMXReg {
1311 uint8_t _b_MMXReg[64 / 8];
1312 uint16_t _w_MMXReg[64 / 16];
1313 uint32_t _l_MMXReg[64 / 32];
1314 uint64_t _q_MMXReg[64 / 64];
1315 float32 _s_MMXReg[64 / 32];
1316 float64 _d_MMXReg[64 / 64];
1317 } MMXReg;
1318
1319 typedef union XMMReg {
1320 uint64_t _q_XMMReg[128 / 64];
1321 } XMMReg;
1322
1323 typedef union YMMReg {
1324 uint64_t _q_YMMReg[256 / 64];
1325 XMMReg _x_YMMReg[256 / 128];
1326 } YMMReg;
1327
1328 typedef union ZMMReg {
1329 uint8_t _b_ZMMReg[512 / 8];
1330 uint16_t _w_ZMMReg[512 / 16];
1331 uint32_t _l_ZMMReg[512 / 32];
1332 uint64_t _q_ZMMReg[512 / 64];
1333 float16 _h_ZMMReg[512 / 16];
1334 float32 _s_ZMMReg[512 / 32];
1335 float64 _d_ZMMReg[512 / 64];
1336 XMMReg _x_ZMMReg[512 / 128];
1337 YMMReg _y_ZMMReg[512 / 256];
1338 } ZMMReg;
1339
1340 typedef struct BNDReg {
1341 uint64_t lb;
1342 uint64_t ub;
1343 } BNDReg;
1344
1345 typedef struct BNDCSReg {
1346 uint64_t cfgu;
1347 uint64_t sts;
1348 } BNDCSReg;
1349
1350 #define BNDCFG_ENABLE 1ULL
1351 #define BNDCFG_BNDPRESERVE 2ULL
1352 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1353
1354 #if HOST_BIG_ENDIAN
1355 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1356 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1357 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1358 #define ZMM_H(n) _h_ZMMReg[31 - (n)]
1359 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1360 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1361 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1362 #define ZMM_X(n) _x_ZMMReg[3 - (n)]
1363 #define ZMM_Y(n) _y_ZMMReg[1 - (n)]
1364
1365 #define XMM_Q(n) _q_XMMReg[1 - (n)]
1366
1367 #define YMM_Q(n) _q_YMMReg[3 - (n)]
1368 #define YMM_X(n) _x_YMMReg[1 - (n)]
1369
1370 #define MMX_B(n) _b_MMXReg[7 - (n)]
1371 #define MMX_W(n) _w_MMXReg[3 - (n)]
1372 #define MMX_L(n) _l_MMXReg[1 - (n)]
1373 #define MMX_S(n) _s_MMXReg[1 - (n)]
1374 #else
1375 #define ZMM_B(n) _b_ZMMReg[n]
1376 #define ZMM_W(n) _w_ZMMReg[n]
1377 #define ZMM_L(n) _l_ZMMReg[n]
1378 #define ZMM_H(n) _h_ZMMReg[n]
1379 #define ZMM_S(n) _s_ZMMReg[n]
1380 #define ZMM_Q(n) _q_ZMMReg[n]
1381 #define ZMM_D(n) _d_ZMMReg[n]
1382 #define ZMM_X(n) _x_ZMMReg[n]
1383 #define ZMM_Y(n) _y_ZMMReg[n]
1384
1385 #define XMM_Q(n) _q_XMMReg[n]
1386
1387 #define YMM_Q(n) _q_YMMReg[n]
1388 #define YMM_X(n) _x_YMMReg[n]
1389
1390 #define MMX_B(n) _b_MMXReg[n]
1391 #define MMX_W(n) _w_MMXReg[n]
1392 #define MMX_L(n) _l_MMXReg[n]
1393 #define MMX_S(n) _s_MMXReg[n]
1394 #endif
1395 #define MMX_Q(n) _q_MMXReg[n]
1396
1397 typedef union {
1398 floatx80 d __attribute__((aligned(16)));
1399 MMXReg mmx;
1400 } FPReg;
1401
1402 typedef struct {
1403 uint64_t base;
1404 uint64_t mask;
1405 } MTRRVar;
1406
1407 #define CPU_NB_REGS64 16
1408 #define CPU_NB_REGS32 8
1409
1410 #ifdef TARGET_X86_64
1411 #define CPU_NB_REGS CPU_NB_REGS64
1412 #else
1413 #define CPU_NB_REGS CPU_NB_REGS32
1414 #endif
1415
1416 #define MAX_FIXED_COUNTERS 3
1417 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1418
1419 #define TARGET_INSN_START_EXTRA_WORDS 1
1420
1421 #define NB_OPMASK_REGS 8
1422
1423 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1424 * that APIC ID hasn't been set yet
1425 */
1426 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1427
1428 typedef struct X86LegacyXSaveArea {
1429 uint16_t fcw;
1430 uint16_t fsw;
1431 uint8_t ftw;
1432 uint8_t reserved;
1433 uint16_t fpop;
1434 union {
1435 struct {
1436 uint64_t fpip;
1437 uint64_t fpdp;
1438 };
1439 struct {
1440 uint32_t fip;
1441 uint32_t fcs;
1442 uint32_t foo;
1443 uint32_t fos;
1444 };
1445 };
1446 uint32_t mxcsr;
1447 uint32_t mxcsr_mask;
1448 FPReg fpregs[8];
1449 uint8_t xmm_regs[16][16];
1450 uint32_t hw_reserved[12];
1451 uint32_t sw_reserved[12];
1452 } X86LegacyXSaveArea;
1453
1454 QEMU_BUILD_BUG_ON(sizeof(X86LegacyXSaveArea) != 512);
1455
1456 typedef struct X86XSaveHeader {
1457 uint64_t xstate_bv;
1458 uint64_t xcomp_bv;
1459 uint64_t reserve0;
1460 uint8_t reserved[40];
1461 } X86XSaveHeader;
1462
1463 /* Ext. save area 2: AVX State */
1464 typedef struct XSaveAVX {
1465 uint8_t ymmh[16][16];
1466 } XSaveAVX;
1467
1468 /* Ext. save area 3: BNDREG */
1469 typedef struct XSaveBNDREG {
1470 BNDReg bnd_regs[4];
1471 } XSaveBNDREG;
1472
1473 /* Ext. save area 4: BNDCSR */
1474 typedef union XSaveBNDCSR {
1475 BNDCSReg bndcsr;
1476 uint8_t data[64];
1477 } XSaveBNDCSR;
1478
1479 /* Ext. save area 5: Opmask */
1480 typedef struct XSaveOpmask {
1481 uint64_t opmask_regs[NB_OPMASK_REGS];
1482 } XSaveOpmask;
1483
1484 /* Ext. save area 6: ZMM_Hi256 */
1485 typedef struct XSaveZMM_Hi256 {
1486 uint8_t zmm_hi256[16][32];
1487 } XSaveZMM_Hi256;
1488
1489 /* Ext. save area 7: Hi16_ZMM */
1490 typedef struct XSaveHi16_ZMM {
1491 uint8_t hi16_zmm[16][64];
1492 } XSaveHi16_ZMM;
1493
1494 /* Ext. save area 9: PKRU state */
1495 typedef struct XSavePKRU {
1496 uint32_t pkru;
1497 uint32_t padding;
1498 } XSavePKRU;
1499
1500 /* Ext. save area 17: AMX XTILECFG state */
1501 typedef struct XSaveXTILECFG {
1502 uint8_t xtilecfg[64];
1503 } XSaveXTILECFG;
1504
1505 /* Ext. save area 18: AMX XTILEDATA state */
1506 typedef struct XSaveXTILEDATA {
1507 uint8_t xtiledata[8][1024];
1508 } XSaveXTILEDATA;
1509
1510 typedef struct {
1511 uint64_t from;
1512 uint64_t to;
1513 uint64_t info;
1514 } LBREntry;
1515
1516 #define ARCH_LBR_NR_ENTRIES 32
1517
1518 /* Ext. save area 19: Supervisor mode Arch LBR state */
1519 typedef struct XSavesArchLBR {
1520 uint64_t lbr_ctl;
1521 uint64_t lbr_depth;
1522 uint64_t ler_from;
1523 uint64_t ler_to;
1524 uint64_t ler_info;
1525 LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1526 } XSavesArchLBR;
1527
1528 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1529 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1530 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1531 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1532 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1533 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1534 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1535 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
1536 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
1537 QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
1538
1539 typedef struct ExtSaveArea {
1540 uint32_t feature, bits;
1541 uint32_t offset, size;
1542 uint32_t ecx;
1543 } ExtSaveArea;
1544
1545 #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1546
1547 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
1548
1549 typedef enum TPRAccess {
1550 TPR_ACCESS_READ,
1551 TPR_ACCESS_WRITE,
1552 } TPRAccess;
1553
1554 /* Cache information data structures: */
1555
1556 enum CacheType {
1557 DATA_CACHE,
1558 INSTRUCTION_CACHE,
1559 UNIFIED_CACHE
1560 };
1561
1562 typedef struct CPUCacheInfo {
1563 enum CacheType type;
1564 uint8_t level;
1565 /* Size in bytes */
1566 uint32_t size;
1567 /* Line size, in bytes */
1568 uint16_t line_size;
1569 /*
1570 * Associativity.
1571 * Note: representation of fully-associative caches is not implemented
1572 */
1573 uint8_t associativity;
1574 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1575 uint8_t partitions;
1576 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1577 uint32_t sets;
1578 /*
1579 * Lines per tag.
1580 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1581 * (Is this synonym to @partitions?)
1582 */
1583 uint8_t lines_per_tag;
1584
1585 /* Self-initializing cache */
1586 bool self_init;
1587 /*
1588 * WBINVD/INVD is not guaranteed to act upon lower level caches of
1589 * non-originating threads sharing this cache.
1590 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1591 */
1592 bool no_invd_sharing;
1593 /*
1594 * Cache is inclusive of lower cache levels.
1595 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1596 */
1597 bool inclusive;
1598 /*
1599 * A complex function is used to index the cache, potentially using all
1600 * address bits. CPUID[4].EDX[bit 2].
1601 */
1602 bool complex_indexing;
1603
1604 /*
1605 * Cache Topology. The level that cache is shared in.
1606 * Used to encode CPUID[4].EAX[bits 25:14] or
1607 * CPUID[0x8000001D].EAX[bits 25:14].
1608 */
1609 enum CPUTopoLevel share_level;
1610 } CPUCacheInfo;
1611
1612
1613 typedef struct CPUCaches {
1614 CPUCacheInfo *l1d_cache;
1615 CPUCacheInfo *l1i_cache;
1616 CPUCacheInfo *l2_cache;
1617 CPUCacheInfo *l3_cache;
1618 } CPUCaches;
1619
1620 typedef struct HVFX86LazyFlags {
1621 target_ulong result;
1622 target_ulong auxbits;
1623 } HVFX86LazyFlags;
1624
1625 typedef struct CPUArchState {
1626 /* standard registers */
1627 target_ulong regs[CPU_NB_REGS];
1628 target_ulong eip;
1629 target_ulong eflags; /* eflags register. During CPU emulation, CC
1630 flags and DF are set to zero because they are
1631 stored elsewhere */
1632
1633 /* emulator internal eflags handling */
1634 target_ulong cc_dst;
1635 target_ulong cc_src;
1636 target_ulong cc_src2;
1637 uint32_t cc_op;
1638 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1639 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1640 are known at translation time. */
1641 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1642
1643 /* segments */
1644 SegmentCache segs[6]; /* selector values */
1645 SegmentCache ldt;
1646 SegmentCache tr;
1647 SegmentCache gdt; /* only base and limit are used */
1648 SegmentCache idt; /* only base and limit are used */
1649
1650 target_ulong cr[5]; /* NOTE: cr1 is unused */
1651
1652 bool pdptrs_valid;
1653 uint64_t pdptrs[4];
1654 int32_t a20_mask;
1655
1656 BNDReg bnd_regs[4];
1657 BNDCSReg bndcs_regs;
1658 uint64_t msr_bndcfgs;
1659 uint64_t efer;
1660
1661 /* Beginning of state preserved by INIT (dummy marker). */
1662 struct {} start_init_save;
1663
1664 /* FPU state */
1665 unsigned int fpstt; /* top of stack index */
1666 uint16_t fpus;
1667 uint16_t fpuc;
1668 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
1669 FPReg fpregs[8];
1670 /* KVM-only so far */
1671 uint16_t fpop;
1672 uint16_t fpcs;
1673 uint16_t fpds;
1674 uint64_t fpip;
1675 uint64_t fpdp;
1676
1677 /* emulator internal variables */
1678 float_status fp_status;
1679 floatx80 ft0;
1680
1681 float_status mmx_status; /* for 3DNow! float ops */
1682 float_status sse_status;
1683 uint32_t mxcsr;
1684 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16);
1685 ZMMReg xmm_t0 QEMU_ALIGNED(16);
1686 MMXReg mmx_t0;
1687
1688 uint64_t opmask_regs[NB_OPMASK_REGS];
1689 #ifdef TARGET_X86_64
1690 uint8_t xtilecfg[64];
1691 uint8_t xtiledata[8192];
1692 #endif
1693
1694 /* sysenter registers */
1695 uint32_t sysenter_cs;
1696 target_ulong sysenter_esp;
1697 target_ulong sysenter_eip;
1698 uint64_t star;
1699
1700 uint64_t vm_hsave;
1701
1702 #ifdef TARGET_X86_64
1703 target_ulong lstar;
1704 target_ulong cstar;
1705 target_ulong fmask;
1706 target_ulong kernelgsbase;
1707 #endif
1708
1709 uint64_t tsc_adjust;
1710 uint64_t tsc_deadline;
1711 uint64_t tsc_aux;
1712
1713 uint64_t xcr0;
1714
1715 uint64_t mcg_status;
1716 uint64_t msr_ia32_misc_enable;
1717 uint64_t msr_ia32_feature_control;
1718 uint64_t msr_ia32_sgxlepubkeyhash[4];
1719
1720 uint64_t msr_fixed_ctr_ctrl;
1721 uint64_t msr_global_ctrl;
1722 uint64_t msr_global_status;
1723 uint64_t msr_global_ovf_ctrl;
1724 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1725 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1726 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1727
1728 uint64_t pat;
1729 uint32_t smbase;
1730 uint64_t msr_smi_count;
1731
1732 uint32_t pkru;
1733 uint32_t pkrs;
1734 uint32_t tsx_ctrl;
1735
1736 uint64_t spec_ctrl;
1737 uint64_t amd_tsc_scale_msr;
1738 uint64_t virt_ssbd;
1739
1740 /* End of state preserved by INIT (dummy marker). */
1741 struct {} end_init_save;
1742
1743 uint64_t system_time_msr;
1744 uint64_t wall_clock_msr;
1745 uint64_t steal_time_msr;
1746 uint64_t async_pf_en_msr;
1747 uint64_t async_pf_int_msr;
1748 uint64_t pv_eoi_en_msr;
1749 uint64_t poll_control_msr;
1750
1751 /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1752 uint64_t msr_hv_hypercall;
1753 uint64_t msr_hv_guest_os_id;
1754 uint64_t msr_hv_tsc;
1755 uint64_t msr_hv_syndbg_control;
1756 uint64_t msr_hv_syndbg_status;
1757 uint64_t msr_hv_syndbg_send_page;
1758 uint64_t msr_hv_syndbg_recv_page;
1759 uint64_t msr_hv_syndbg_pending_page;
1760 uint64_t msr_hv_syndbg_options;
1761
1762 /* Per-VCPU HV MSRs */
1763 uint64_t msr_hv_vapic;
1764 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1765 uint64_t msr_hv_runtime;
1766 uint64_t msr_hv_synic_control;
1767 uint64_t msr_hv_synic_evt_page;
1768 uint64_t msr_hv_synic_msg_page;
1769 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1770 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1771 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1772 uint64_t msr_hv_reenlightenment_control;
1773 uint64_t msr_hv_tsc_emulation_control;
1774 uint64_t msr_hv_tsc_emulation_status;
1775
1776 uint64_t msr_rtit_ctrl;
1777 uint64_t msr_rtit_status;
1778 uint64_t msr_rtit_output_base;
1779 uint64_t msr_rtit_output_mask;
1780 uint64_t msr_rtit_cr3_match;
1781 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1782
1783 /* Per-VCPU XFD MSRs */
1784 uint64_t msr_xfd;
1785 uint64_t msr_xfd_err;
1786
1787 /* Per-VCPU Arch LBR MSRs */
1788 uint64_t msr_lbr_ctl;
1789 uint64_t msr_lbr_depth;
1790 LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1791
1792 /* exception/interrupt handling */
1793 int error_code;
1794 int exception_is_int;
1795 target_ulong exception_next_eip;
1796 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1797 union {
1798 struct CPUBreakpoint *cpu_breakpoint[4];
1799 struct CPUWatchpoint *cpu_watchpoint[4];
1800 }; /* break/watchpoints for dr[0..3] */
1801 int old_exception; /* exception in flight */
1802
1803 uint64_t vm_vmcb;
1804 uint64_t tsc_offset;
1805 uint64_t intercept;
1806 uint16_t intercept_cr_read;
1807 uint16_t intercept_cr_write;
1808 uint16_t intercept_dr_read;
1809 uint16_t intercept_dr_write;
1810 uint32_t intercept_exceptions;
1811 uint64_t nested_cr3;
1812 uint32_t nested_pg_mode;
1813 uint8_t v_tpr;
1814 uint32_t int_ctl;
1815
1816 /* KVM states, automatically cleared on reset */
1817 uint8_t nmi_injected;
1818 uint8_t nmi_pending;
1819
1820 uintptr_t retaddr;
1821
1822 /* Fields up to this point are cleared by a CPU reset */
1823 struct {} end_reset_fields;
1824
1825 /* Fields after this point are preserved across CPU reset. */
1826
1827 /* processor features (e.g. for CPUID insn) */
1828 /* Minimum cpuid leaf 7 value */
1829 uint32_t cpuid_level_func7;
1830 /* Actual cpuid leaf 7 value */
1831 uint32_t cpuid_min_level_func7;
1832 /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1833 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1834 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1835 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1836 /* Actual level/xlevel/xlevel2 value: */
1837 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1838 uint32_t cpuid_vendor1;
1839 uint32_t cpuid_vendor2;
1840 uint32_t cpuid_vendor3;
1841 uint32_t cpuid_version;
1842 FeatureWordArray features;
1843 /* Features that were explicitly enabled/disabled */
1844 FeatureWordArray user_features;
1845 uint32_t cpuid_model[12];
1846 /* Cache information for CPUID. When legacy-cache=on, the cache data
1847 * on each CPUID leaf will be different, because we keep compatibility
1848 * with old QEMU versions.
1849 */
1850 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1851
1852 /* MTRRs */
1853 uint64_t mtrr_fixed[11];
1854 uint64_t mtrr_deftype;
1855 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1856
1857 /* For KVM */
1858 uint32_t mp_state;
1859 int32_t exception_nr;
1860 int32_t interrupt_injected;
1861 uint8_t soft_interrupt;
1862 uint8_t exception_pending;
1863 uint8_t exception_injected;
1864 uint8_t has_error_code;
1865 uint8_t exception_has_payload;
1866 uint64_t exception_payload;
1867 uint8_t triple_fault_pending;
1868 uint32_t ins_len;
1869 uint32_t sipi_vector;
1870 bool tsc_valid;
1871 int64_t tsc_khz;
1872 int64_t user_tsc_khz; /* for sanity check only */
1873 uint64_t apic_bus_freq;
1874 uint64_t tsc;
1875 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1876 void *xsave_buf;
1877 uint32_t xsave_buf_len;
1878 #endif
1879 #if defined(CONFIG_KVM)
1880 struct kvm_nested_state *nested_state;
1881 MemoryRegion *xen_vcpu_info_mr;
1882 void *xen_vcpu_info_hva;
1883 uint64_t xen_vcpu_info_gpa;
1884 uint64_t xen_vcpu_info_default_gpa;
1885 uint64_t xen_vcpu_time_info_gpa;
1886 uint64_t xen_vcpu_runstate_gpa;
1887 uint8_t xen_vcpu_callback_vector;
1888 bool xen_callback_asserted;
1889 uint16_t xen_virq[XEN_NR_VIRQS];
1890 uint64_t xen_singleshot_timer_ns;
1891 QEMUTimer *xen_singleshot_timer;
1892 uint64_t xen_periodic_timer_period;
1893 QEMUTimer *xen_periodic_timer;
1894 QemuMutex xen_timers_lock;
1895 #endif
1896 #if defined(CONFIG_HVF)
1897 HVFX86LazyFlags hvf_lflags;
1898 void *hvf_mmio_buf;
1899 #endif
1900
1901 uint64_t mcg_cap;
1902 uint64_t mcg_ctl;
1903 uint64_t mcg_ext_ctl;
1904 uint64_t mce_banks[MCE_BANKS_DEF*4];
1905 uint64_t xstate_bv;
1906
1907 /* vmstate */
1908 uint16_t fpus_vmstate;
1909 uint16_t fptag_vmstate;
1910 uint16_t fpregs_format_vmstate;
1911
1912 uint64_t xss;
1913 uint32_t umwait;
1914
1915 TPRAccess tpr_access_type;
1916
1917 /* Number of dies within this CPU package. */
1918 unsigned nr_dies;
1919
1920 /* Number of modules within one die. */
1921 unsigned nr_modules;
1922
1923 /* Bitmap of available CPU topology levels for this CPU. */
1924 DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX);
1925 } CPUX86State;
1926
1927 struct kvm_msrs;
1928
1929 /**
1930 * X86CPU:
1931 * @env: #CPUX86State
1932 * @migratable: If set, only migratable flags will be accepted when "enforce"
1933 * mode is used, and only migratable flags will be included in the "host"
1934 * CPU model.
1935 *
1936 * An x86 CPU.
1937 */
1938 struct ArchCPU {
1939 CPUState parent_obj;
1940
1941 CPUX86State env;
1942 VMChangeStateEntry *vmsentry;
1943
1944 uint64_t ucode_rev;
1945
1946 uint32_t hyperv_spinlock_attempts;
1947 char *hyperv_vendor;
1948 bool hyperv_synic_kvm_only;
1949 uint64_t hyperv_features;
1950 bool hyperv_passthrough;
1951 OnOffAuto hyperv_no_nonarch_cs;
1952 uint32_t hyperv_vendor_id[3];
1953 uint32_t hyperv_interface_id[4];
1954 uint32_t hyperv_limits[3];
1955 bool hyperv_enforce_cpuid;
1956 uint32_t hyperv_ver_id_build;
1957 uint16_t hyperv_ver_id_major;
1958 uint16_t hyperv_ver_id_minor;
1959 uint32_t hyperv_ver_id_sp;
1960 uint8_t hyperv_ver_id_sb;
1961 uint32_t hyperv_ver_id_sn;
1962
1963 bool check_cpuid;
1964 bool enforce_cpuid;
1965 /*
1966 * Force features to be enabled even if the host doesn't support them.
1967 * This is dangerous and should be done only for testing CPUID
1968 * compatibility.
1969 */
1970 bool force_features;
1971 bool expose_kvm;
1972 bool expose_tcg;
1973 bool migratable;
1974 bool migrate_smi_count;
1975 bool max_features; /* Enable all supported features automatically */
1976 uint32_t apic_id;
1977
1978 /* Enables publishing of TSC increment and Local APIC bus frequencies to
1979 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1980 bool vmware_cpuid_freq;
1981
1982 /* if true the CPUID code directly forward host cache leaves to the guest */
1983 bool cache_info_passthrough;
1984
1985 /* if true the CPUID code directly forwards
1986 * host monitor/mwait leaves to the guest */
1987 struct {
1988 uint32_t eax;
1989 uint32_t ebx;
1990 uint32_t ecx;
1991 uint32_t edx;
1992 } mwait;
1993
1994 /* Features that were filtered out because of missing host capabilities */
1995 FeatureWordArray filtered_features;
1996
1997 /* Enable PMU CPUID bits. This can't be enabled by default yet because
1998 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1999 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
2000 * capabilities) directly to the guest.
2001 */
2002 bool enable_pmu;
2003
2004 /*
2005 * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR.
2006 * This can't be initialized with a default because it doesn't have
2007 * stable ABI support yet. It is only allowed to pass all LBR_FMT bits
2008 * returned by kvm_arch_get_supported_msr_feature()(which depends on both
2009 * host CPU and kernel capabilities) to the guest.
2010 */
2011 uint64_t lbr_fmt;
2012
2013 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
2014 * disabled by default to avoid breaking migration between QEMU with
2015 * different LMCE configurations.
2016 */
2017 bool enable_lmce;
2018
2019 /* Compatibility bits for old machine types.
2020 * If true present virtual l3 cache for VM, the vcpus in the same virtual
2021 * socket share an virtual l3 cache.
2022 */
2023 bool enable_l3_cache;
2024
2025 /* Compatibility bits for old machine types.
2026 * If true present L1 cache as per-thread, not per-core.
2027 */
2028 bool l1_cache_per_core;
2029
2030 /* Compatibility bits for old machine types.
2031 * If true present the old cache topology information
2032 */
2033 bool legacy_cache;
2034
2035 /* Compatibility bits for old machine types.
2036 * If true decode the CPUID Function 0x8000001E_ECX to support multiple
2037 * nodes per processor
2038 */
2039 bool legacy_multi_node;
2040
2041 /* Compatibility bits for old machine types: */
2042 bool enable_cpuid_0xb;
2043
2044 /* Enable auto level-increase for all CPUID leaves */
2045 bool full_cpuid_auto_level;
2046
2047 /* Only advertise CPUID leaves defined by the vendor */
2048 bool vendor_cpuid_only;
2049
2050 /* Enable auto level-increase for Intel Processor Trace leave */
2051 bool intel_pt_auto_level;
2052
2053 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
2054 bool fill_mtrr_mask;
2055
2056 /* if true override the phys_bits value with a value read from the host */
2057 bool host_phys_bits;
2058
2059 /* if set, limit maximum value for phys_bits when host_phys_bits is true */
2060 uint8_t host_phys_bits_limit;
2061
2062 /* Stop SMI delivery for migration compatibility with old machines */
2063 bool kvm_no_smi_migration;
2064
2065 /* Forcefully disable KVM PV features not exposed in guest CPUIDs */
2066 bool kvm_pv_enforce_cpuid;
2067
2068 /* Number of physical address bits supported */
2069 uint32_t phys_bits;
2070
2071 /*
2072 * Number of guest physical address bits available. Usually this is
2073 * identical to host physical address bits. With NPT or EPT 4-level
2074 * paging, guest physical address space might be restricted to 48 bits
2075 * even if the host cpu supports more physical address bits.
2076 */
2077 uint32_t guest_phys_bits;
2078
2079 /* in order to simplify APIC support, we leave this pointer to the
2080 user */
2081 struct DeviceState *apic_state;
2082 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
2083 Notifier machine_done;
2084
2085 struct kvm_msrs *kvm_msr_buf;
2086
2087 int32_t node_id; /* NUMA node this CPU belongs to */
2088 int32_t socket_id;
2089 int32_t die_id;
2090 int32_t module_id;
2091 int32_t core_id;
2092 int32_t thread_id;
2093
2094 int32_t hv_max_vps;
2095
2096 bool xen_vapic;
2097 };
2098
2099 typedef struct X86CPUModel X86CPUModel;
2100
2101 /**
2102 * X86CPUClass:
2103 * @cpu_def: CPU model definition
2104 * @host_cpuid_required: Whether CPU model requires cpuid from host.
2105 * @ordering: Ordering on the "-cpu help" CPU model list.
2106 * @migration_safe: See CpuDefinitionInfo::migration_safe
2107 * @static_model: See CpuDefinitionInfo::static
2108 * @parent_realize: The parent class' realize handler.
2109 * @parent_phases: The parent class' reset phase handlers.
2110 *
2111 * An x86 CPU model or family.
2112 */
2113 struct X86CPUClass {
2114 CPUClass parent_class;
2115
2116 /*
2117 * CPU definition, automatically loaded by instance_init if not NULL.
2118 * Should be eventually replaced by subclass-specific property defaults.
2119 */
2120 X86CPUModel *model;
2121
2122 bool host_cpuid_required;
2123 int ordering;
2124 bool migration_safe;
2125 bool static_model;
2126
2127 /*
2128 * Optional description of CPU model.
2129 * If unavailable, cpu_def->model_id is used.
2130 */
2131 const char *model_description;
2132
2133 DeviceRealize parent_realize;
2134 DeviceUnrealize parent_unrealize;
2135 ResettablePhases parent_phases;
2136 };
2137
2138 #ifndef CONFIG_USER_ONLY
2139 extern const VMStateDescription vmstate_x86_cpu;
2140 #endif
2141
2142 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
2143
2144 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
2145 int cpuid, DumpState *s);
2146 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
2147 int cpuid, DumpState *s);
2148 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2149 DumpState *s);
2150 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2151 DumpState *s);
2152
2153 bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
2154 Error **errp);
2155
2156 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
2157
2158 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
2159 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
2160
2161 void x86_cpu_list(void);
2162 int cpu_x86_support_mca_broadcast(CPUX86State *env);
2163
2164 #ifndef CONFIG_USER_ONLY
2165 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
2166 MemTxAttrs *attrs);
2167 int cpu_get_pic_interrupt(CPUX86State *s);
2168
2169 /* MS-DOS compatibility mode FPU exception support */
2170 void x86_register_ferr_irq(qemu_irq irq);
2171 void fpu_check_raise_ferr_irq(CPUX86State *s);
2172 void cpu_set_ignne(void);
2173 void cpu_clear_ignne(void);
2174 #endif
2175
2176 /* mpx_helper.c */
2177 void cpu_sync_bndcs_hflags(CPUX86State *env);
2178
2179 /* this function must always be used to load data in the segment
2180 cache: it synchronizes the hflags with the segment cache values */
cpu_x86_load_seg_cache(CPUX86State * env,X86Seg seg_reg,unsigned int selector,target_ulong base,unsigned int limit,unsigned int flags)2181 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
2182 X86Seg seg_reg, unsigned int selector,
2183 target_ulong base,
2184 unsigned int limit,
2185 unsigned int flags)
2186 {
2187 SegmentCache *sc;
2188 unsigned int new_hflags;
2189
2190 sc = &env->segs[seg_reg];
2191 sc->selector = selector;
2192 sc->base = base;
2193 sc->limit = limit;
2194 sc->flags = flags;
2195
2196 /* update the hidden flags */
2197 {
2198 if (seg_reg == R_CS) {
2199 #ifdef TARGET_X86_64
2200 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
2201 /* long mode */
2202 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2203 env->hflags &= ~(HF_ADDSEG_MASK);
2204 } else
2205 #endif
2206 {
2207 /* legacy / compatibility case */
2208 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
2209 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
2210 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
2211 new_hflags;
2212 }
2213 }
2214 if (seg_reg == R_SS) {
2215 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
2216 #if HF_CPL_MASK != 3
2217 #error HF_CPL_MASK is hardcoded
2218 #endif
2219 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
2220 /* Possibly switch between BNDCFGS and BNDCFGU */
2221 cpu_sync_bndcs_hflags(env);
2222 }
2223 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
2224 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
2225 if (env->hflags & HF_CS64_MASK) {
2226 /* zero base assumed for DS, ES and SS in long mode */
2227 } else if (!(env->cr[0] & CR0_PE_MASK) ||
2228 (env->eflags & VM_MASK) ||
2229 !(env->hflags & HF_CS32_MASK)) {
2230 /* XXX: try to avoid this test. The problem comes from the
2231 fact that is real mode or vm86 mode we only modify the
2232 'base' and 'selector' fields of the segment cache to go
2233 faster. A solution may be to force addseg to one in
2234 translate-i386.c. */
2235 new_hflags |= HF_ADDSEG_MASK;
2236 } else {
2237 new_hflags |= ((env->segs[R_DS].base |
2238 env->segs[R_ES].base |
2239 env->segs[R_SS].base) != 0) <<
2240 HF_ADDSEG_SHIFT;
2241 }
2242 env->hflags = (env->hflags &
2243 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
2244 }
2245 }
2246
cpu_x86_load_seg_cache_sipi(X86CPU * cpu,uint8_t sipi_vector)2247 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
2248 uint8_t sipi_vector)
2249 {
2250 CPUState *cs = CPU(cpu);
2251 CPUX86State *env = &cpu->env;
2252
2253 env->eip = 0;
2254 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
2255 sipi_vector << 12,
2256 env->segs[R_CS].limit,
2257 env->segs[R_CS].flags);
2258 cs->halted = 0;
2259 }
2260
2261 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
2262 target_ulong *base, unsigned int *limit,
2263 unsigned int *flags);
2264
2265 /* op_helper.c */
2266 /* used for debug or cpu save/restore */
2267
2268 /* cpu-exec.c */
2269 /*
2270 * The following helpers are only usable in user mode simulation.
2271 * The host pointers should come from lock_user().
2272 */
2273 void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector);
2274 void cpu_x86_fsave(CPUX86State *s, void *host, size_t len);
2275 void cpu_x86_frstor(CPUX86State *s, void *host, size_t len);
2276 void cpu_x86_fxsave(CPUX86State *s, void *host, size_t len);
2277 void cpu_x86_fxrstor(CPUX86State *s, void *host, size_t len);
2278 void cpu_x86_xsave(CPUX86State *s, void *host, size_t len, uint64_t rbfm);
2279 bool cpu_x86_xrstor(CPUX86State *s, void *host, size_t len, uint64_t rbfm);
2280
2281 /* cpu.c */
2282 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
2283 uint32_t vendor2, uint32_t vendor3);
2284 typedef struct PropValue {
2285 const char *prop, *value;
2286 } PropValue;
2287 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
2288
2289 void x86_cpu_after_reset(X86CPU *cpu);
2290
2291 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env);
2292
2293 /* cpu.c other functions (cpuid) */
2294 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2295 uint32_t *eax, uint32_t *ebx,
2296 uint32_t *ecx, uint32_t *edx);
2297 void cpu_clear_apic_feature(CPUX86State *env);
2298 void cpu_set_apic_feature(CPUX86State *env);
2299 void host_cpuid(uint32_t function, uint32_t count,
2300 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
2301 bool cpu_has_x2apic_feature(CPUX86State *env);
2302
2303 /* helper.c */
2304 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
2305 void cpu_sync_avx_hflag(CPUX86State *env);
2306
2307 #ifndef CONFIG_USER_ONLY
x86_asidx_from_attrs(CPUState * cs,MemTxAttrs attrs)2308 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2309 {
2310 return !!attrs.secure;
2311 }
2312
cpu_addressspace(CPUState * cs,MemTxAttrs attrs)2313 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
2314 {
2315 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
2316 }
2317
2318 /*
2319 * load efer and update the corresponding hflags. XXX: do consistency
2320 * checks with cpuid bits?
2321 */
2322 void cpu_load_efer(CPUX86State *env, uint64_t val);
2323 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
2324 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
2325 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
2326 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
2327 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
2328 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
2329 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
2330 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
2331 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
2332 #endif
2333
2334 /* will be suppressed */
2335 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
2336 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
2337 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
2338 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
2339
2340 /* hw/pc.c */
2341 uint64_t cpu_get_tsc(CPUX86State *env);
2342
2343 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
2344
2345 #ifdef TARGET_X86_64
2346 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2347 #else
2348 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2349 #endif
2350
2351 #define cpu_list x86_cpu_list
2352
2353 /* MMU modes definitions */
2354 #define MMU_KSMAP64_IDX 0
2355 #define MMU_KSMAP32_IDX 1
2356 #define MMU_USER64_IDX 2
2357 #define MMU_USER32_IDX 3
2358 #define MMU_KNOSMAP64_IDX 4
2359 #define MMU_KNOSMAP32_IDX 5
2360 #define MMU_PHYS_IDX 6
2361 #define MMU_NESTED_IDX 7
2362
2363 #ifdef CONFIG_USER_ONLY
2364 #ifdef TARGET_X86_64
2365 #define MMU_USER_IDX MMU_USER64_IDX
2366 #else
2367 #define MMU_USER_IDX MMU_USER32_IDX
2368 #endif
2369 #endif
2370
is_mmu_index_smap(int mmu_index)2371 static inline bool is_mmu_index_smap(int mmu_index)
2372 {
2373 return (mmu_index & ~1) == MMU_KSMAP64_IDX;
2374 }
2375
is_mmu_index_user(int mmu_index)2376 static inline bool is_mmu_index_user(int mmu_index)
2377 {
2378 return (mmu_index & ~1) == MMU_USER64_IDX;
2379 }
2380
is_mmu_index_32(int mmu_index)2381 static inline bool is_mmu_index_32(int mmu_index)
2382 {
2383 assert(mmu_index < MMU_PHYS_IDX);
2384 return mmu_index & 1;
2385 }
2386
cpu_mmu_index_kernel(CPUX86State * env)2387 static inline int cpu_mmu_index_kernel(CPUX86State *env)
2388 {
2389 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1;
2390 int mmu_index_base =
2391 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX :
2392 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX;
2393
2394 return mmu_index_base + mmu_index_32;
2395 }
2396
2397 #define CC_DST (env->cc_dst)
2398 #define CC_SRC (env->cc_src)
2399 #define CC_SRC2 (env->cc_src2)
2400 #define CC_OP (env->cc_op)
2401
2402 #include "exec/cpu-all.h"
2403 #include "svm.h"
2404
2405 #if !defined(CONFIG_USER_ONLY)
2406 #include "hw/i386/apic.h"
2407 #endif
2408
cpu_get_tb_cpu_state(CPUX86State * env,vaddr * pc,uint64_t * cs_base,uint32_t * flags)2409 static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
2410 uint64_t *cs_base, uint32_t *flags)
2411 {
2412 *flags = env->hflags |
2413 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2414 if (env->hflags & HF_CS64_MASK) {
2415 *cs_base = 0;
2416 *pc = env->eip;
2417 } else {
2418 *cs_base = env->segs[R_CS].base;
2419 *pc = (uint32_t)(*cs_base + env->eip);
2420 }
2421 }
2422
2423 void do_cpu_init(X86CPU *cpu);
2424
2425 #define MCE_INJECT_BROADCAST 1
2426 #define MCE_INJECT_UNCOND_AO 2
2427
2428 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2429 uint64_t status, uint64_t mcg_status, uint64_t addr,
2430 uint64_t misc, int flags);
2431
2432 uint32_t cpu_cc_compute_all(CPUX86State *env1);
2433
cpu_compute_eflags(CPUX86State * env)2434 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2435 {
2436 uint32_t eflags = env->eflags;
2437 if (tcg_enabled()) {
2438 eflags |= cpu_cc_compute_all(env) | (env->df & DF_MASK);
2439 }
2440 return eflags;
2441 }
2442
cpu_get_mem_attrs(CPUX86State * env)2443 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2444 {
2445 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2446 }
2447
x86_get_a20_mask(CPUX86State * env)2448 static inline int32_t x86_get_a20_mask(CPUX86State *env)
2449 {
2450 if (env->hflags & HF_SMM_MASK) {
2451 return -1;
2452 } else {
2453 return env->a20_mask;
2454 }
2455 }
2456
cpu_has_vmx(CPUX86State * env)2457 static inline bool cpu_has_vmx(CPUX86State *env)
2458 {
2459 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2460 }
2461
cpu_has_svm(CPUX86State * env)2462 static inline bool cpu_has_svm(CPUX86State *env)
2463 {
2464 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2465 }
2466
2467 /*
2468 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2469 * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2470 * VMX operation. This is because CR4.VMXE is one of the bits set
2471 * in MSR_IA32_VMX_CR4_FIXED1.
2472 *
2473 * There is one exception to above statement when vCPU enters SMM mode.
2474 * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2475 * may also reset CR4.VMXE during execution in SMM mode.
2476 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2477 * and CR4.VMXE is restored to it's original value of being set.
2478 *
2479 * Therefore, when vCPU is not in SMM mode, we can infer whether
2480 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2481 * know for certain.
2482 */
cpu_vmx_maybe_enabled(CPUX86State * env)2483 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2484 {
2485 return cpu_has_vmx(env) &&
2486 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2487 }
2488
2489 /* excp_helper.c */
2490 int get_pg_mode(CPUX86State *env);
2491
2492 /* fpu_helper.c */
2493 void update_fp_status(CPUX86State *env);
2494 void update_mxcsr_status(CPUX86State *env);
2495 void update_mxcsr_from_sse_status(CPUX86State *env);
2496
cpu_set_mxcsr(CPUX86State * env,uint32_t mxcsr)2497 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2498 {
2499 env->mxcsr = mxcsr;
2500 if (tcg_enabled()) {
2501 update_mxcsr_status(env);
2502 }
2503 }
2504
cpu_set_fpuc(CPUX86State * env,uint16_t fpuc)2505 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2506 {
2507 env->fpuc = fpuc;
2508 if (tcg_enabled()) {
2509 update_fp_status(env);
2510 }
2511 }
2512
2513 /* svm_helper.c */
2514 #ifdef CONFIG_USER_ONLY
2515 static inline void
cpu_svm_check_intercept_param(CPUX86State * env1,uint32_t type,uint64_t param,uintptr_t retaddr)2516 cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2517 uint64_t param, uintptr_t retaddr)
2518 { /* no-op */ }
2519 static inline bool
cpu_svm_has_intercept(CPUX86State * env,uint32_t type)2520 cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
2521 { return false; }
2522 #else
2523 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2524 uint64_t param, uintptr_t retaddr);
2525 bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type);
2526 #endif
2527
2528 /* apic.c */
2529 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2530 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2531 TPRAccess access);
2532
2533 /* Special values for X86CPUVersion: */
2534
2535 /* Resolve to latest CPU version */
2536 #define CPU_VERSION_LATEST -1
2537
2538 /*
2539 * Resolve to version defined by current machine type.
2540 * See x86_cpu_set_default_version()
2541 */
2542 #define CPU_VERSION_AUTO -2
2543
2544 /* Don't resolve to any versioned CPU models, like old QEMU versions */
2545 #define CPU_VERSION_LEGACY 0
2546
2547 typedef int X86CPUVersion;
2548
2549 /*
2550 * Set default CPU model version for CPU models having
2551 * version == CPU_VERSION_AUTO.
2552 */
2553 void x86_cpu_set_default_version(X86CPUVersion version);
2554
2555 #ifndef CONFIG_USER_ONLY
2556
2557 void do_cpu_sipi(X86CPU *cpu);
2558
2559 #define APIC_DEFAULT_ADDRESS 0xfee00000
2560 #define APIC_SPACE_SIZE 0x100000
2561
2562 /* cpu-dump.c */
2563 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2564
2565 #endif
2566
2567 /* cpu.c */
2568 bool cpu_is_bsp(X86CPU *cpu);
2569
2570 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen);
2571 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen);
2572 uint32_t xsave_area_size(uint64_t mask, bool compacted);
2573 void x86_update_hflags(CPUX86State* env);
2574
hyperv_feat_enabled(X86CPU * cpu,int feat)2575 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2576 {
2577 return !!(cpu->hyperv_features & BIT(feat));
2578 }
2579
cr4_reserved_bits(CPUX86State * env)2580 static inline uint64_t cr4_reserved_bits(CPUX86State *env)
2581 {
2582 uint64_t reserved_bits = CR4_RESERVED_MASK;
2583 if (!env->features[FEAT_XSAVE]) {
2584 reserved_bits |= CR4_OSXSAVE_MASK;
2585 }
2586 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) {
2587 reserved_bits |= CR4_SMEP_MASK;
2588 }
2589 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
2590 reserved_bits |= CR4_SMAP_MASK;
2591 }
2592 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) {
2593 reserved_bits |= CR4_FSGSBASE_MASK;
2594 }
2595 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
2596 reserved_bits |= CR4_PKE_MASK;
2597 }
2598 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) {
2599 reserved_bits |= CR4_LA57_MASK;
2600 }
2601 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
2602 reserved_bits |= CR4_UMIP_MASK;
2603 }
2604 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
2605 reserved_bits |= CR4_PKS_MASK;
2606 }
2607 if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) {
2608 reserved_bits |= CR4_LAM_SUP_MASK;
2609 }
2610 return reserved_bits;
2611 }
2612
ctl_has_irq(CPUX86State * env)2613 static inline bool ctl_has_irq(CPUX86State *env)
2614 {
2615 uint32_t int_prio;
2616 uint32_t tpr;
2617
2618 int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
2619 tpr = env->int_ctl & V_TPR_MASK;
2620
2621 if (env->int_ctl & V_IGN_TPR_MASK) {
2622 return (env->int_ctl & V_IRQ_MASK);
2623 }
2624
2625 return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
2626 }
2627
2628 #if defined(TARGET_X86_64) && \
2629 defined(CONFIG_USER_ONLY) && \
2630 defined(CONFIG_LINUX)
2631 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2632 #endif
2633
2634 #endif /* I386_CPU_H */
2635