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Searched refs:MXL_RV32 (Results 1 – 24 of 24) sorted by relevance

/qemu/target/riscv/
H A Dtranslate.c127 #define get_xl(ctx) MXL_RV32
150 #define get_ol(ctx) MXL_RV32
162 #define get_xl_max(ctx) MXL_RV32
331 case MXL_RV32: in get_gpr()
385 case MXL_RV32: in gen_set_gpr()
406 case MXL_RV32: in gen_set_gpri()
442 case MXL_RV32: in get_fpr_hs()
469 case MXL_RV32: in get_fpr_d()
495 case MXL_RV32: in dest_fpr()
515 case MXL_RV32: in gen_set_fpr_hs()
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H A Dcpu.c60 return riscv_cpu_mxl(&cpu->env) == MXL_RV32; in riscv_cpu_is_32bit()
408 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; in set_satp_mode_max_supported()
444 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? in riscv_any_cpu_init()
887 if (env->xl == MXL_RV32) { in riscv_cpu_set_pc()
900 if (env->xl == MXL_RV32) { in riscv_cpu_get_pc()
946 if (env->misa_mxl > MXL_RV32) { in riscv_cpu_reset_hold()
1035 case MXL_RV32: in riscv_cpu_disas_set_info()
1231 if (cpu->env.misa_mxl == MXL_RV32) { in riscv_add_satp_mode_properties()
1422 case MXL_RV32: in riscv_cpu_validate_misa_mxl()
2154 case MXL_RV32: in prop_marchid_set()
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H A Dcpu.h580 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
614 if (xl != MXL_RV32) { in cpu_get_xl()
631 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
644 #define cpu_address_xl(env) ((void)(env), MXL_RV32)
664 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
H A Dgdbstub.c66 case MXL_RV32: in riscv_cpu_gdb_read_register()
86 case MXL_RV32: in riscv_cpu_gdb_write_register()
348 case MXL_RV32: in riscv_cpu_register_gdb_regs_for_features()
H A Dmonitor.c156 if (riscv_cpu_mxl(env) == MXL_RV32) { in mem_info_svxx()
226 if (riscv_cpu_mxl(env) == MXL_RV32) { in hmp_info_mem()
H A Dcsr.c165 if (riscv_cpu_mxl(env) != MXL_RV32) { in ctr32()
214 if (riscv_cpu_mxl(env) != MXL_RV32) { in mctr32()
237 if (riscv_cpu_mxl(env) != MXL_RV32) { in any32()
274 if (riscv_cpu_mxl(env) != MXL_RV32) { in smode32()
310 if (riscv_cpu_mxl(env) != MXL_RV32) { in hmode32()
329 if (riscv_cpu_mxl(env) != MXL_RV32) { in umode32()
458 if (riscv_cpu_mxl(env) != MXL_RV32) { in sstc_32()
664 case MXL_RV32: in read_vtype()
838 if (riscv_cpu_mxl(env) == MXL_RV32) { in write_mhpmevent()
1276 case MXL_RV32: in add_status_sd()
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H A Dcommon-semi-target.h35 return riscv_cpu_mxl(env) != MXL_RV32; in is_64bit_semihosting()
H A Dpmu.c201 if (riscv_cpu_mxl(env) == MXL_RV32) { in riscv_pmu_incr_ctr()
349 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_timer_trigger_irq()
H A Dcpu_helper.c73 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; in cpu_get_tb_cpu_state()
188 if (xl == MXL_RV32) { in riscv_cpu_update_mask()
843 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
851 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
861 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
970 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
980 if (riscv_cpu_sxl(env) == MXL_RV32) { in get_physical_address()
H A Ddebug.c81 case MXL_RV32: in extract_trigger_type()
137 case MXL_RV32: in build_tdata1()
185 case MXL_RV32: in tdata1_validate()
H A Dcpu_bits.h559 MXL_RV32 = 1, enumerator
H A Dop_helper.c64 target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; in helper_csrw()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvzacas.c.inc48 assert(get_ol(ctx) == MXL_RV32);
61 assert(get_ol(ctx) == MXL_RV32);
103 case MXL_RV32:
H A Dtrans_rvi.c.inc62 if (get_xl(ctx) == MXL_RV32) {
686 ctx->ol = MXL_RV32;
693 ctx->ol = MXL_RV32;
700 ctx->ol = MXL_RV32;
707 ctx->ol = MXL_RV32;
735 ctx->ol = MXL_RV32;
742 ctx->ol = MXL_RV32;
749 ctx->ol = MXL_RV32;
756 ctx->ol = MXL_RV32;
763 ctx->ol = MXL_RV32;
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H A Dtrans_rvm.c.inc326 ctx->ol = MXL_RV32;
334 ctx->ol = MXL_RV32;
342 ctx->ol = MXL_RV32;
350 ctx->ol = MXL_RV32;
358 ctx->ol = MXL_RV32;
H A Dtrans_rvb.c.inc385 ctx->ol = MXL_RV32;
393 ctx->ol = MXL_RV32;
401 ctx->ol = MXL_RV32;
409 ctx->ol = MXL_RV32;
417 ctx->ol = MXL_RV32;
H A Dtrans_rvzce.c.inc178 MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ;
223 MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ;
H A Dtrans_xthead.c.inc153 ctx->ol = MXL_RV32;
515 ctx->ol = MXL_RV32;
524 ctx->ol = MXL_RV32;
539 ctx->ol = MXL_RV32;
548 ctx->ol = MXL_RV32;
H A Dtrans_rvd.c.inc28 if (ctx->cfg_ptr->ext_zdinx && (get_xl(ctx) == MXL_RV32) && \
H A Dtrans_rvv.c.inc303 if (get_xl(s) == MXL_RV32) {
2043 if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
/qemu/linux-user/riscv/
H A Dtarget_proc.h19 mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48"; in open_cpuinfo()
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c101 if (xl == MXL_RV32) { in riscv_cpu_synchronize_from_tb()
124 if (xl == MXL_RV32) { in riscv_restore_state_to_opc()
579 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { in riscv_cpu_validate_set_extensions()
587 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { in riscv_cpu_validate_set_extensions()
595 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions()
1329 if (env->misa_mxl != MXL_RV32) { in riscv_init_max_cpu_extensions()
/qemu/hw/riscv/
H A Dboot.c40 return mcc->misa_mxl_max == MXL_RV32; in riscv_is_32bit()
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c67 case MXL_RV32: in kvm_riscv_reg_id_ulong()
1458 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { in kvm_riscv_handle_sbi_dbcn()
1957 mcc->misa_mxl_max = MXL_RV32; in riscv_host_cpu_class_init()