/qemu/target/riscv/ |
H A D | translate.c | 127 #define get_xl(ctx) MXL_RV32 150 #define get_ol(ctx) MXL_RV32 162 #define get_xl_max(ctx) MXL_RV32 331 case MXL_RV32: in get_gpr() 385 case MXL_RV32: in gen_set_gpr() 406 case MXL_RV32: in gen_set_gpri() 442 case MXL_RV32: in get_fpr_hs() 469 case MXL_RV32: in get_fpr_d() 495 case MXL_RV32: in dest_fpr() 515 case MXL_RV32: in gen_set_fpr_hs() [all …]
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H A D | cpu.c | 60 return riscv_cpu_mxl(&cpu->env) == MXL_RV32; in riscv_cpu_is_32bit() 408 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; in set_satp_mode_max_supported() 444 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? in riscv_any_cpu_init() 887 if (env->xl == MXL_RV32) { in riscv_cpu_set_pc() 900 if (env->xl == MXL_RV32) { in riscv_cpu_get_pc() 946 if (env->misa_mxl > MXL_RV32) { in riscv_cpu_reset_hold() 1035 case MXL_RV32: in riscv_cpu_disas_set_info() 1231 if (cpu->env.misa_mxl == MXL_RV32) { in riscv_add_satp_mode_properties() 1422 case MXL_RV32: in riscv_cpu_validate_misa_mxl() 2154 case MXL_RV32: in prop_marchid_set() [all …]
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H A D | cpu.h | 580 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 614 if (xl != MXL_RV32) { in cpu_get_xl() 631 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 644 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 664 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
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H A D | gdbstub.c | 66 case MXL_RV32: in riscv_cpu_gdb_read_register() 86 case MXL_RV32: in riscv_cpu_gdb_write_register() 348 case MXL_RV32: in riscv_cpu_register_gdb_regs_for_features()
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H A D | monitor.c | 156 if (riscv_cpu_mxl(env) == MXL_RV32) { in mem_info_svxx() 226 if (riscv_cpu_mxl(env) == MXL_RV32) { in hmp_info_mem()
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H A D | csr.c | 165 if (riscv_cpu_mxl(env) != MXL_RV32) { in ctr32() 214 if (riscv_cpu_mxl(env) != MXL_RV32) { in mctr32() 237 if (riscv_cpu_mxl(env) != MXL_RV32) { in any32() 274 if (riscv_cpu_mxl(env) != MXL_RV32) { in smode32() 310 if (riscv_cpu_mxl(env) != MXL_RV32) { in hmode32() 329 if (riscv_cpu_mxl(env) != MXL_RV32) { in umode32() 458 if (riscv_cpu_mxl(env) != MXL_RV32) { in sstc_32() 664 case MXL_RV32: in read_vtype() 838 if (riscv_cpu_mxl(env) == MXL_RV32) { in write_mhpmevent() 1276 case MXL_RV32: in add_status_sd() [all …]
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H A D | common-semi-target.h | 35 return riscv_cpu_mxl(env) != MXL_RV32; in is_64bit_semihosting()
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H A D | pmu.c | 201 if (riscv_cpu_mxl(env) == MXL_RV32) { in riscv_pmu_incr_ctr() 349 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_timer_trigger_irq()
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H A D | cpu_helper.c | 73 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; in cpu_get_tb_cpu_state() 188 if (xl == MXL_RV32) { in riscv_cpu_update_mask() 843 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address() 851 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address() 861 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address() 970 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address() 980 if (riscv_cpu_sxl(env) == MXL_RV32) { in get_physical_address()
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H A D | debug.c | 81 case MXL_RV32: in extract_trigger_type() 137 case MXL_RV32: in build_tdata1() 185 case MXL_RV32: in tdata1_validate()
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H A D | cpu_bits.h | 559 MXL_RV32 = 1, enumerator
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H A D | op_helper.c | 64 target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; in helper_csrw()
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/qemu/target/riscv/insn_trans/ |
H A D | trans_rvzacas.c.inc | 48 assert(get_ol(ctx) == MXL_RV32); 61 assert(get_ol(ctx) == MXL_RV32); 103 case MXL_RV32:
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H A D | trans_rvi.c.inc | 62 if (get_xl(ctx) == MXL_RV32) { 686 ctx->ol = MXL_RV32; 693 ctx->ol = MXL_RV32; 700 ctx->ol = MXL_RV32; 707 ctx->ol = MXL_RV32; 735 ctx->ol = MXL_RV32; 742 ctx->ol = MXL_RV32; 749 ctx->ol = MXL_RV32; 756 ctx->ol = MXL_RV32; 763 ctx->ol = MXL_RV32; [all …]
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H A D | trans_rvm.c.inc | 326 ctx->ol = MXL_RV32; 334 ctx->ol = MXL_RV32; 342 ctx->ol = MXL_RV32; 350 ctx->ol = MXL_RV32; 358 ctx->ol = MXL_RV32;
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H A D | trans_rvb.c.inc | 385 ctx->ol = MXL_RV32; 393 ctx->ol = MXL_RV32; 401 ctx->ol = MXL_RV32; 409 ctx->ol = MXL_RV32; 417 ctx->ol = MXL_RV32;
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H A D | trans_rvzce.c.inc | 178 MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ; 223 MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ;
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H A D | trans_xthead.c.inc | 153 ctx->ol = MXL_RV32; 515 ctx->ol = MXL_RV32; 524 ctx->ol = MXL_RV32; 539 ctx->ol = MXL_RV32; 548 ctx->ol = MXL_RV32;
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H A D | trans_rvd.c.inc | 28 if (ctx->cfg_ptr->ext_zdinx && (get_xl(ctx) == MXL_RV32) && \
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H A D | trans_rvv.c.inc | 303 if (get_xl(s) == MXL_RV32) { 2043 if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
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/qemu/linux-user/riscv/ |
H A D | target_proc.h | 19 mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48"; in open_cpuinfo()
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/qemu/target/riscv/tcg/ |
H A D | tcg-cpu.c | 101 if (xl == MXL_RV32) { in riscv_cpu_synchronize_from_tb() 124 if (xl == MXL_RV32) { in riscv_restore_state_to_opc() 579 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { in riscv_cpu_validate_set_extensions() 587 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { in riscv_cpu_validate_set_extensions() 595 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions() 1329 if (env->misa_mxl != MXL_RV32) { in riscv_init_max_cpu_extensions()
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/qemu/hw/riscv/ |
H A D | boot.c | 40 return mcc->misa_mxl_max == MXL_RV32; in riscv_is_32bit()
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/qemu/target/riscv/kvm/ |
H A D | kvm-cpu.c | 67 case MXL_RV32: in kvm_riscv_reg_id_ulong() 1458 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { in kvm_riscv_handle_sbi_dbcn() 1957 mcc->misa_mxl_max = MXL_RV32; in riscv_host_cpu_class_init()
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