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Searched refs:NVP2_W1_CO_THRID (Results 1 – 2 of 2) sorted by relevance

/qemu/hw/intc/
H A Dxive2.c163 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); in xive2_nvp_pic_print_info()
246 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { in xive2_tctx_save_os_ctx()
260 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); in xive2_tctx_save_os_ctx()
327 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); in xive2_tctx_restore_os_ctx()
/qemu/include/hw/ppc/
H A Dxive2_regs.h158 #define NVP2_W1_CO_THRID PPC_BITMASK32(17, 31) macro