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Searched refs:NVP2_W1_CO_THRID (Results 1 – 3 of 3) sorted by relevance

/qemu/include/hw/ppc/
H A Dxive2_regs.h151 #define NVP2_W1_CO_THRID PPC_BITMASK32(17, 31) macro
/qemu/hw/intc/
H A Dxive2.c218 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { in xive2_tctx_save_os_ctx()
232 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); in xive2_tctx_save_os_ctx()
299 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); in xive2_tctx_restore_os_ctx()
H A Dpnv_xive2.c2050 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); in type_init()