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Searched refs:OPC_RISC_STORE (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dinstmap.h31 OPC_RISC_STORE = (0x23), enumerator
142 OPC_RISC_SB = OPC_RISC_STORE | (0x0 << 12),
143 OPC_RISC_SH = OPC_RISC_STORE | (0x1 << 12),
144 OPC_RISC_SW = OPC_RISC_STORE | (0x2 << 12),
145 OPC_RISC_SD = OPC_RISC_STORE | (0x3 << 12),
H A Dcpu_helper.c1613 case OPC_RISC_STORE: in riscv_transformed_insn()