Searched refs:POWER (Results 1 – 11 of 11) sorted by relevance
13 FSI allows a service processor access to the internal buses of a host POWER14 processor to perform configuration or debugging. FSI has long existed in POWER18 Working backwards from the POWER processor, the fundamental pieces of interest22 "engines" that drive accesses on buses internal and external to the POWER33 driving CFAM engine accesses into the POWER chip. At the hardware level37 4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER110 pdbg is a simple application to allow debugging of the host POWER processors
41 * POWER Protected Execution Facility (PEF) (see :ref:`power-papr-protected-execution-facility-pef`)
110 docs: powerpc: Document nested KVM on POWER112 Document support for nested KVM on POWER using the existing API as well
10 a POWER and an x86 board can run the same code to emulate a PCI network
36 #define POWER(n) (n + POWER0) macro269 int idx = POWER(i); in atmega_realize()
15 implementation for certain IBM POWER hardware. The sources are at
189 /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
2 * PMU register read/write functions for TCG IBM POWER chips
1202 ## Misc POWER instructions
258 POWER (PAPR) Protected Execution Facility (PEF)
853 ``compat`` property of server class POWER CPUs (removed in 6.0)