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Searched refs:R1 (Results 1 – 7 of 7) sorted by relevance

/qemu/target/avr/
H A Dtranslate.c713 TCGv R1 = cpu_r[1]; in trans_MUL() local
720 tcg_gen_shri_tl(R1, R, 8); in trans_MUL()
738 TCGv R1 = cpu_r[1]; in trans_MULS() local
750 tcg_gen_shri_tl(R1, R, 8); in trans_MULS()
769 TCGv R1 = cpu_r[1]; in trans_MULSU() local
798 TCGv R1 = cpu_r[1]; in trans_FMUL() local
813 tcg_gen_andi_tl(R1, R1, 0xff); in trans_FMUL()
828 TCGv R1 = cpu_r[1]; in trans_FMULS() local
848 tcg_gen_andi_tl(R1, R1, 0xff); in trans_FMULS()
863 TCGv R1 = cpu_r[1]; in trans_FMULSU() local
[all …]
/qemu/tests/tcg/multiarch/
H A Dsha1.c64 #define R1(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk(i)+0x5A827999+rol(v,5);w=rol(w,30); macro
101 R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); in SHA1Transform()
/qemu/target/hexagon/idef-parser/
H A DREADME.rst561 to diverge on line 141, with an incorrect value in the ``R1`` register
604 58 | 0x00021090: 0x9182c001 { R1 = memw(R2+#0x0) }
605 59 | 0x00021094: 0xf302c101 { R1 = add(R2,R1) }
622 here. Next we may notice that ``R1`` is only touched by lines 57 and 58, that is
627 58 | 0x00021090: 0x9182c001 { R1 = memw(R2+#0x0) }
628 59 | 0x00021094: 0xf302c101 { R1 = add(R2,R1) }
631 ``R1 = memw(R2+#0x0)`` or with an incorrect add ``R1 = add(R2,R1)``. At this
/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc51 easy way to compress the fields has R1 and B1 overlap. */
/qemu/target/mips/
H A Dcpu-defs.c.inc862 .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */
/qemu/tcg/arm/
H A Dtcg-target.c.inc1460 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
1461 * Load the tlb comparator into R2/R3 and the fast path addend into R1.
/qemu/tcg/s390x/
H A Dtcg-target.c.inc1502 result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */