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Searched refs:REG_MBOX0_RDCLR (Results 1 – 1 of 1) sorted by relevance

/qemu/hw/intc/
H A Dbcm2836_control.c36 #define REG_MBOX0_RDCLR 0xc0 macro
266 } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) { in bcm2836_control_read()
267 return s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2]; in bcm2836_control_read()
293 } else if (offset >= REG_MBOX0_WR && offset < REG_MBOX0_RDCLR) { in bcm2836_control_write()
295 } else if (offset >= REG_MBOX0_RDCLR && offset < REG_LIMIT) { in bcm2836_control_write()
296 s->mailboxes[(offset - REG_MBOX0_RDCLR) >> 2] &= ~val; in bcm2836_control_write()