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Searched refs:REG_MCMDR (Results 1 – 3 of 3) sorted by relevance

/qemu/hw/net/
H A Dnpcm7xx_emc.c141 uint32_t mcmdr = emc->regs[REG_MCMDR]; in emc_soft_reset()
143 emc->regs[REG_MCMDR] = mcmdr & (REG_MCMDR_LBK | REG_MCMDR_OPMOD); in emc_soft_reset()
543 if (emc->regs[REG_MCMDR] & REG_MCMDR_ALP) { in emc_receive()
571 if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { in emc_receive()
582 (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC) && in emc_receive()
598 if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { in emc_receive()
692 case REG_MCMDR: { in npcm7xx_emc_write()
752 if (emc->regs[REG_MCMDR] & REG_MCMDR_TXON) { in npcm7xx_emc_write()
761 if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { in npcm7xx_emc_write()
/qemu/tests/qtest/
H A Dnpcm7xx_emc-test.c60 REG_MCMDR, enumerator
308 emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR); in emc_soft_reset()
324 val = emc_read(qts, mod, REG_MCMDR); in emc_soft_reset()
357 CHECK_REG(REG_MCMDR, 0); in test_init()
489 uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR); in enable_tx()
491 emc_write(qts, mod, REG_MCMDR, mcmdr); in enable_tx()
640 uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR); in enable_rx()
642 emc_write(qts, mod, REG_MCMDR, mcmdr); in enable_rx()
/qemu/include/hw/net/
H A Dnpcm7xx_emc.h37 REG_MCMDR, enumerator