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Searched refs:RISCV_PMU_EVENT_HW_INSTRUCTIONS (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dpmu.c227 event_idx = RISCV_PMU_EVENT_HW_INSTRUCTIONS; in riscv_pmu_ctr_monitor_instructions()
313 case RISCV_PMU_EVENT_HW_INSTRUCTIONS: in riscv_pmu_update_event_map()
339 evt_idx != RISCV_PMU_EVENT_HW_INSTRUCTIONS) { in pmu_timer_trigger_irq()
382 pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS); in riscv_pmu_timer_cb()
H A Dcpu.h778 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, enumerator