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Searched refs:R_CTRL (Results 1 – 5 of 5) sorted by relevance

/qemu/hw/dma/
H A Dxlnx-zynq-devcfg.c202 val |= lock_ctrl_map[i] & s->regs[R_CTRL]; in r_ctrl_pre_write()
227 s->regs[R_CTRL] |= R_CTRL_PCAP_PR_MASK; in r_unlock_post_write()
228 s->regs[R_CTRL] |= R_CTRL_PCFG_AES_EN_MASK; in r_unlock_post_write()
232 s->regs[R_CTRL] &= ~R_CTRL_PCAP_PR_MASK; in r_unlock_post_write()
233 s->regs[R_CTRL] &= ~R_CTRL_PCFG_AES_EN_MASK; in r_unlock_post_write()
H A Dxlnx_csu_dma.c121 paused = !!(s->regs[R_CTRL] & R_CTRL_PAUSE_STRM_MASK); in xlnx_csu_dma_is_paused()
122 paused |= !!(s->regs[R_CTRL] & R_CTRL_PAUSE_MEM_MASK); in xlnx_csu_dma_is_paused()
134 return !!(s->regs[R_CTRL] & R_CTRL_AXI_BRST_TYPE_MASK); in xlnx_csu_dma_burst_is_fixed()
156 bswap = s->regs[R_CTRL] & R_CTRL_ENDIANNESS_MASK; in xlnx_csu_dma_data_process()
/qemu/hw/char/
H A Dxilinx_uartlite.c41 #define R_CTRL 3 macro
78 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE); in uart_update_irq()
141 case R_CTRL: in uart_write()
H A Dibex_uart.c283 case R_CTRL: in ibex_uart_read()
366 case R_CTRL: in ibex_uart_write()
/qemu/hw/timer/
H A Dibex_timer.c147 case R_CTRL: in ibex_timer_read()
194 case R_CTRL: in ibex_timer_write()