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Searched refs:SEED_OPST_ES16 (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h876 #define SEED_OPST_ES16 (0b10 << 30) macro
H A Dcsr.c4292 rval = random_v | SEED_OPST_ES16; in riscv_new_csr_seed()