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Searched refs:SET_RS2 (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dcpu_helper.c1489 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn()
1497 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn()
1505 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn()
1511 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn()
1557 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); in riscv_transformed_insn()
1565 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); in riscv_transformed_insn()
1573 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); in riscv_transformed_insn()
1579 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); in riscv_transformed_insn()
H A Dinstmap.h324 #define SET_RS2(inst, val) deposit32(inst, 20, 5, val) macro