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Searched refs:SHAMT (Results 1 – 8 of 8) sorted by relevance

/qemu/target/hexagon/idef-parser/
H A Dmacros.inc44 (fCAST##REGSTYPE##s(SRC) >> -SHAMT))
46 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \
49 (fCAST##REGSTYPE##u(SRC) >>> -SHAMT))
54 (fCAST##REGSTYPE##s(SRC) << -SHAMT))
56 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
57 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
61 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
122 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> SHAMT)
123 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) (SRC >>> SHAMT)
124 #define fROTL(SRC, SHAMT, REGSTYPE) fROTL(SRC, SHAMT)
[all …]
/qemu/target/hexagon/
H A Dmacros.h483 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
490 (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
493 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
503 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT))
504 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \
505 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT)))
506 #define fROTL(SRC, SHAMT, REGSTYPE) \
507 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
510 #define fROTR(SRC, SHAMT, REGSTYPE) \
511 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
[all …]
/qemu/target/hexagon/imported/
H A Dmacros.def988 …(((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT))-1)) >>1) : (fCAST##REGSTYPE(SRC) << (SHAMT)…
994 fBIDIR_SHIFTL(SRC,SHAMT,REGSTYPE##s),
1000 fBIDIR_SHIFTL(SRC,SHAMT,REGSTYPE##u),
1006 …(((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT))-1)) >>1) : fSAT_ORIG_SHL(fCAST##REGSTYPE…
1013 …(((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT))-1)) << 1) : (fCAST##REGSTYPE(SRC) >> (SHAMT…
1019 fBIDIR_SHIFTR(SRC,SHAMT,REGSTYPE##s),
1031 …(((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) << ((-(SHAMT))-1)) << 1,(SRC)) : (fCAST##R…
1043 (((SHAMT) >= 64)?0:(fCAST##REGSTYPE##u(SRC) >> (SHAMT))),
1049 (((SHAMT)==0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
1056 (((SHAMT)==0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
[all …]
/qemu/target/riscv/insn_trans/
H A Dtrans_rvb.c.inc336 #define GEN_SHADD(SHAMT) \
337 static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
341 tcg_gen_shli_tl(t, arg1, SHAMT); \
350 static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
421 #define GEN_SHADD_UW(SHAMT) \
422 static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
428 tcg_gen_shli_tl(t, t, SHAMT); \
436 #define GEN_TRANS_SHADD_UW(SHAMT) \
437 static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
438 arg_sh##SHAMT##add_uw *a) \
[all …]
H A Dtrans_xthead.c.inc114 #define GEN_TH_ADDSL(SHAMT) \
115 static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \
118 tcg_gen_shli_tl(t, arg2, SHAMT); \
126 #define GEN_TRANS_TH_ADDSL(SHAMT) \
127 static bool trans_th_addsl##SHAMT(DisasContext *ctx, \
128 arg_th_addsl##SHAMT * a) \
131 return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \
/qemu/tests/tcg/hexagon/
H A Dv69_hvx.c28 #define fVROUND(VAL, SHAMT) \ argument
29 ((VAL) + (((SHAMT) > 0) ? (1LL << ((SHAMT) - 1)) : 0))
/qemu/target/hexagon/mmvec/
H A Dmacros.h339 #define fVNOROUND(VAL, SHAMT) VAL
341 #define fVROUND(VAL, SHAMT) \
342 ((VAL) + (((SHAMT) > 0) ? (1LL << ((SHAMT) - 1)) : 0))
/qemu/target/hexagon/imported/mmvec/
H A Dmacros.def825 ((VAL) + (((SHAMT)>0)?(1LL<<((SHAMT)-1)):0)),