| /qemu/target/arm/tcg/ |
| H A D | iwmmxt_helper.c | 82 #define SADB(SHR) abs((int) ((a >> SHR) & 0xff) - (int) ((b >> SHR) & 0xff)) in HELPER() argument
91 #define SADW(SHR) \ in HELPER() argument
92 abs((int) ((a >> SHR) & 0xffff) - (int) ((b >> SHR) & 0xffff)) in HELPER()
118 ((a >> SHR) & 0xffff) * ((b >> SHR) & 0xffff) \ in HELPER()
127 ((a >> SHR) & 0xffff) * ((b >> SHR) & 0xffff) \ in HELPER()
135 #define MACS(SHR) ( \ in HELPER() argument
136 EXTEND16((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff)) in HELPER()
313 OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR)
319 OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR)
328 ((a >> SHR) & 0xff) + ((b >> SHR) & 0xff) + round) >> 1) << SHR)
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| /qemu/target/i386/ |
| H A D | ops_sse.h | 1554 d->Q(0) = SHR(s->Q(0), shift - 0) | in SSE_HELPER_W()
1555 SHR(v->Q(0), shift - 64); in SSE_HELPER_W()
1560 r0 = SHR(s->Q(i), shift - 0) | in SSE_HELPER_W()
1561 SHR(s->Q(i + 1), shift - 64) | in SSE_HELPER_W()
1562 SHR(v->Q(i), shift - 128) | in SSE_HELPER_W()
1563 SHR(v->Q(i + 1), shift - 192); in SSE_HELPER_W()
1564 r1 = SHR(s->Q(i), shift + 64) | in SSE_HELPER_W()
1565 SHR(s->Q(i + 1), shift - 0) | in SSE_HELPER_W()
1566 SHR(v->Q(i), shift - 64) | in SSE_HELPER_W()
1567 SHR(v->Q(i + 1), shift - 128); in SSE_HELPER_W()
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| /qemu/target/i386/tcg/ |
| H A D | emit.c.inc | 2860 * SHR/RCR/SHR/RCR/... is a relatively common occurrence of RCR.
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| /qemu/tests/tcg/i386/ |
| H A D | x86.csv | 14 # 1. The Intel manual instruction mnemonic. For example, "SHR r/m32, imm8".
31 # the Intel mnemonic. For example, "rw,r" to denote that "SHR r/m32, imm8"
1961 "SHR r/m8, 1","SHRB 1, r/m8","shrb 1, r/m8","D0 /5","V","V","","","rw,r","Y","8"
1962 "SHR r/m8, 1","SHRB 1, r/m8","shrb 1, r/m8","REX D0 /5","N.E.","V","","pseudo64","rw,r","Y","8"
1963 "SHR r/m8, CL","SHRB CL, r/m8","shrb CL, r/m8","D2 /5","V","V","","","rw,r","Y","8"
1966 "SHR r/m8, imm8u","SHRB imm8u, r/m8","shrb imm8u, r/m8","C0 /5 ib","V","V","","","rw,r","Y","8"
1967 "SHR r/m32, 1","SHRL 1, r/m32","shrl 1, r/m32","D1 /5","V","V","","operand32","rw,r","Y","32"
1968 "SHR r/m32, CL","SHRL CL, r/m32","shrl CL, r/m32","D3 /5","V","V","","operand32","rw,r","Y","32"
1972 "SHR r/m64, 1","SHRQ 1, r/m64","shrq 1, r/m64","REX.W D1 /5","N.S.","V","","","rw,r","Y","64"
1973 "SHR r/m64, CL","SHRQ CL, r/m64","shrq CL, r/m64","REX.W D3 /5","N.S.","V","","","rw,r","Y","64"
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