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Searched refs:SIFIVE_E_DEV_DTIM (Results 1 – 2 of 2) sorted by relevance

/qemu/hw/riscv/
H A Dsifive_e.c71 [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
96 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); in sifive_e_machine_init()
119 memmap[SIFIVE_E_DEV_DTIM].base, in sifive_e_machine_init()
154 mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size; in sifive_e_machine_class_init()
/qemu/include/hw/riscv/
H A Dsifive_e.h77 SIFIVE_E_DEV_DTIM enumerator