Home
last modified time | relevance | path

Searched refs:SMSTATEEN0_FCSR (Results 1 – 3 of 3) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h316 #define SMSTATEEN0_FCSR (1ULL << 1) macro
H A Dcsr.c88 return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); in fs()
2245 wr_mask |= SMSTATEEN0_FCSR; in write_mstateen0()
2321 wr_mask |= SMSTATEEN0_FCSR; in write_hstateen0()
2411 wr_mask |= SMSTATEEN0_FCSR; in write_sstateen0()
H A Dcpu_helper.c129 fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) in cpu_get_tb_cpu_state()