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Searched refs:SNVS_LPSRTCMR (Results 1 – 2 of 2) sorted by relevance

/qemu/hw/misc/
H A Dimx7_snvs.c53 case SNVS_LPSRTCMR: in imx7_snvs_read()
85 if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) { in imx7_snvs_write()
90 case SNVS_LPSRTCMR: in imx7_snvs_write()
108 if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) { in imx7_snvs_write()
/qemu/include/hw/misc/
H A Dimx7_snvs.h24 SNVS_LPSRTCMR = 0x050, /* Secure Real Time Counter MSB Register */ enumerator