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Searched refs:SPR_MPC_MI_DBRAM0 (Results 1 – 2 of 2) sorted by relevance

/qemu/target/ppc/
H A Dcpu.h2080 #define SPR_MPC_MI_DBRAM0 (0x321) macro
H A Dcpu_init.c1548 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", in register_8xx_sprs()