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Searched refs:SSCR0_RIM (Results 1 – 1 of 1) sorted by relevance

/qemu/hw/arm/
H A Dpxa2xx.c549 #define SSCR0_RIM (1 << 22) macro
588 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); in pxa2xx_ssp_int_update()