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Searched refs:SSCR0_TIM (Results 1 – 1 of 1) sorted by relevance

/qemu/hw/arm/
H A Dpxa2xx.c550 #define SSCR0_TIM (1 << 23) macro
584 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); in pxa2xx_ssp_int_update()