Home
last modified time | relevance | path

Searched refs:TCG_COND_GEU (Results 1 – 25 of 40) sorted by relevance

12

/qemu/include/tcg/
H A Dtcg-cond.h57 TCG_COND_GEU = 8 | 0 | 2 | 1, enumerator
125 case TCG_COND_GEU: in tcg_high_cond()
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_branch.c.inc80 TRANS(bgeu, ALL, gen_rr_bc, TCG_COND_GEU)
/qemu/tcg/
H A Doptimize.c629 case TCG_COND_GEU: in do_constant_folding_cond_32()
663 case TCG_COND_GEU: in do_constant_folding_cond_64()
690 case TCG_COND_GEU: in do_constant_folding_cond_eq()
732 case TCG_COND_GEU: in do_constant_folding_cond()
888 case TCG_COND_GEU: in do_constant_folding_cond2()
2133 case TCG_COND_GEU: in fold_setcond_zmask()
2159 case TCG_COND_GEU: in fold_setcond_zmask()
H A Dtci.c223 case TCG_COND_GEU: in tci_compare32()
271 case TCG_COND_GEU: in tci_compare64()
1054 [TCG_COND_GEU] = "geu", in str_c()
/qemu/tcg/sparc64/
H A Dtcg-target.c.inc620 [TCG_COND_GEU] = COND_CC,
733 case TCG_COND_GEU:
747 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
756 cond = (cond == TCG_COND_TSTEQ ? TCG_COND_GEU : TCG_COND_LTU);
881 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0);
896 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst);
/qemu/accel/tcg/
H A Dplugin-gen.c151 return TCG_COND_GEU; in plugin_cond_to_tcgcond()
/qemu/target/riscv/
H A Dtranslate.c196 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); in gen_check_nanbox_h()
204 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); in gen_check_nanbox_s()
/qemu/target/tricore/
H A Dtranslate.c1471 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); in gen_sub_CC()
3036 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, in gen_compute_branch()
5073 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5145 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], in decode_rc_accumulator()
5181 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); in decode_rc_accumulator()
5663 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5703 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5811 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5847 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
5900 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], in decode_rr_accumulator()
[all …]
/qemu/target/hexagon/idef-parser/
H A Didef-parser.y650 $$ = gen_bin_cmp(c, &@1, TCG_COND_GEU, &$1, &$3);
/qemu/tcg/ppc/
H A Dtcg-target.c.inc318 case TCG_COND_GEU:
731 [TCG_COND_GEU] = BC | BI(0, CR_LT) | BO_COND_FALSE,
747 [TCG_COND_GEU] = ISEL | BC_(0, CR_LT) | 1,
1836 case TCG_COND_GEU:
2050 case TCG_COND_GEU:
2185 [TCG_COND_GEU] = { CR_GT, CR_LT },
2234 case TCG_COND_GEU:
3951 case TCG_COND_GEU:
/qemu/target/hexagon/
H A Dgen_tcg.h1064 gen_cmp_jumpnv(ctx, TCG_COND_GEU, NsN, RtV, riV)
1066 gen_cmp_jumpnv(ctx, TCG_COND_GEU, NsN, RtV, riV)
/qemu/tcg/s390x/
H A Dtcg-target.c.inc426 [TCG_COND_GEU] = S390_CC_GE,
444 [TCG_COND_GEU] = S390_CC_ALWAYS,
578 case TCG_COND_GEU:
1324 case TCG_COND_GEU:
1370 case TCG_COND_GEU:
3062 case TCG_COND_GEU:
/qemu/target/openrisc/
H A Dtranslate.c960 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, in trans_l_sfgeu()
1027 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R(dc, a->a), a->i); in trans_l_sfgeui()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvi.c.inc126 case TCG_COND_GEU:
226 return gen_branch(ctx, a, TCG_COND_GEU);
/qemu/tcg/i386/
H A Dtcg-target.c.inc520 [TCG_COND_GEU] = JCC_JAE,
1613 tcg_out_brcond(s, 0, TCG_COND_GEU, args[0], args[2], const_args[2],
1637 case TCG_COND_GEU:
1641 tcg_out_brcond(s, 0, TCG_COND_GEU, args[0], args[2], const_args[2],
1697 case TCG_COND_GEU:
4024 case TCG_COND_GEU:
/qemu/target/arm/tcg/
H A Dgengvec.c1078 tcg_gen_cmp_vec(TCG_COND_GEU, vece, lsh, lsh, max); in gen_ushl_vec()
1079 tcg_gen_cmp_vec(TCG_COND_GEU, vece, rsh, rsh, max); in gen_ushl_vec()
H A Dtranslate-sve.c2419 tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last); in incr_last_active()
3124 cond = eq ? TCG_COND_GEU : TCG_COND_GTU; in trans_WHILE()
3205 tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, diff, t1); in trans_WHILE_ptr()
3216 tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, tmax, diff); in trans_WHILE_ptr()
/qemu/tcg/arm/
H A Dtcg-target.c.inc249 [TCG_COND_GEU] = COND_CS,
1238 case TCG_COND_GEU:
2593 [TCG_COND_GEU] = INSN_VCGE_U,
/qemu/target/ppc/
H A Dtranslate.c1932 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); in gen_op_arith_subf()
4333 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); in gen_setb()
4334 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); in gen_setb()
4880 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); in gen_405_mulladd_insn()
/qemu/tcg/riscv/
H A Dtcg-target.c.inc780 [TCG_COND_GEU] = { OPC_BGEU, false },
814 case TCG_COND_GEU: /* -> LTU */
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc370 [TCG_COND_GEU] = COND_HS,
2524 [TCG_COND_GEU] = I3616_CMHS,
2531 [TCG_COND_GEU] = I3611_CMHS,
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc571 case TCG_COND_GEU: /* -> LTU */
725 [TCG_COND_GEU] = { OPC_BLEU, true },
/qemu/target/microblaze/
H A Dtranslate.c538 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_msr_c, inb, ina); in DO_TYPEA_CFG()
/qemu/docs/devel/
H A Dtcg-ops.rst253 | ``TCG_COND_GEU /* unsigned */``
/qemu/target/sh4/
H A Dtranslate.c739 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()

12