/qemu/target/hexagon/ |
H A D | gen_tcg_hvx.h | 440 fGEN_TCG_VEC_CMP(TCG_COND_GTU, MO_32, 4) 442 fGEN_TCG_VEC_CMP(TCG_COND_GTU, MO_16, 2) 444 fGEN_TCG_VEC_CMP(TCG_COND_GTU, MO_8, 1) 471 fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_and) 473 fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_or) 475 fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_xor) 485 fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_and) 487 fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_or) 499 fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_and) 501 fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_or) [all …]
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H A D | gen_tcg.h | 795 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 797 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 799 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 801 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 803 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 805 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 807 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 1069 gen_cmpi_jumpnv(ctx, TCG_COND_GTU, NsN, UiV, riV) 1071 gen_cmpi_jumpnv(ctx, TCG_COND_GTU, NsN, UiV, riV) 1078 gen_cmp_jumpnv(ctx, TCG_COND_GTU, NsN, RtV, riV) [all …]
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H A D | genptr.c | 1366 tcg_gen_movcond_tl(TCG_COND_GTU, tmp, source, max_val, max_val, source); in gen_satu_i32() 1403 tcg_gen_movcond_i64(TCG_COND_GTU, tmp, source, max_val, max_val, source); in gen_satu_i64()
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/qemu/include/tcg/ |
H A D | tcg-cond.h | 58 TCG_COND_GTU = 8 | 4 | 2 | 0, enumerator
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/qemu/accel/tcg/ |
H A D | plugin-gen.c | 150 return TCG_COND_GTU; in plugin_cond_to_tcgcond()
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/qemu/tcg/ |
H A D | tci.c | 229 case TCG_COND_GTU: in tci_compare32() 277 case TCG_COND_GTU: in tci_compare64() 1056 [TCG_COND_GTU] = "gtu", in str_c()
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H A D | optimize.c | 633 case TCG_COND_GTU: in do_constant_folding_cond_32() 667 case TCG_COND_GTU: in do_constant_folding_cond_64() 686 case TCG_COND_GTU: in do_constant_folding_cond_eq() 2132 case TCG_COND_GTU: in fold_setcond_zmask()
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H A D | tcg-op-vec.c | 667 do_minmax(vece, r, a, b, INDEX_op_umax_vec, TCG_COND_GTU); in tcg_gen_umax_vec()
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/qemu/target/ppc/translate/ |
H A D | vmx-impl.c.inc | 1230 TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8) 1231 TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16) 1232 TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32) 1233 TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64) 1338 tcg_gen_negsetcond_i64(TCG_COND_GTU, t2, t0, t1); 1343 tcg_gen_negsetcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t1, t0, t1); 1377 tcg_gen_brcond_i64((sign ? TCG_COND_GT : TCG_COND_GTU), vra, vrb, gt); 1382 tcg_gen_brcond_i64(TCG_COND_GTU, vra, vrb, gt);
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H A D | spe-impl.c.inc | 288 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
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/qemu/tcg/s390x/ |
H A D | tcg-target.c.inc | 425 [TCG_COND_GTU] = S390_CC_GT, 443 [TCG_COND_GTU] = S390_CC_NE, 580 case TCG_COND_GTU: 1326 case TCG_COND_GTU: 1390 cond = TCG_COND_GTU; 1396 case TCG_COND_GTU: 2969 case TCG_COND_GTU: 3050 case TCG_COND_GTU:
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/qemu/tcg/ppc/ |
H A D | tcg-target.c.inc | 320 case TCG_COND_GTU: 733 [TCG_COND_GTU] = BC | BI(0, CR_GT) | BO_COND_TRUE, 749 [TCG_COND_GTU] = ISEL | BC_(0, CR_GT), 1838 case TCG_COND_GTU: 2045 case TCG_COND_GTU: 2184 [TCG_COND_GTU] = { CR_GT, CR_GT }, 2233 case TCG_COND_GTU: 3851 case TCG_COND_GTU: 3935 case TCG_COND_GTU:
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/qemu/target/hexagon/idef-parser/ |
H A D | idef-parser.y | 626 $$ = gen_bin_cmp(c, &@1, TCG_COND_GTU, &$1, &$3);
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H A D | parser-helpers.c | 2064 case TCG_COND_GTU: in cond_to_str()
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/qemu/tcg/i386/ |
H A D | tcg-target.c.inc | 522 [TCG_COND_GTU] = JCC_JA, 1606 tcg_out_brcond(s, 0, TCG_COND_GTU, args[0], args[2], const_args[2], 1630 case TCG_COND_GTU: 1631 tcg_out_brcond(s, 0, TCG_COND_GTU, args[1], args[3], const_args[3], 1634 tcg_out_brcond(s, 0, TCG_COND_GTU, args[0], args[2], const_args[2], 1638 tcg_out_brcond(s, 0, TCG_COND_GTU, args[1], args[3], const_args[3], 1687 case TCG_COND_GTU: 4017 case TCG_COND_GTU:
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/qemu/target/openrisc/ |
H A D | translate.c | 953 tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, in trans_l_sfgtu() 1021 tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R(dc, a->a), a->i); in trans_l_sfgtui()
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/qemu/target/mips/tcg/ |
H A D | mxu_translate.c | 3471 tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t1); in gen_mxu_d32add() 3474 tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t2); in gen_mxu_d32add() 3484 tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t1); in gen_mxu_d32add() 3487 tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t2); in gen_mxu_d32add()
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/qemu/tcg/sparc64/ |
H A D | tcg-target.c.inc | 622 [TCG_COND_GTU] = COND_GU, 759 case TCG_COND_GTU:
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/qemu/tcg/arm/ |
H A D | tcg-target.c.inc | 251 [TCG_COND_GTU] = COND_HI, 1237 case TCG_COND_GTU: 2592 [TCG_COND_GTU] = INSN_VCGT_U,
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/qemu/tcg/riscv/ |
H A D | tcg-target.c.inc | 796 [TCG_COND_GTU] = { OPC_BLTU, true } 830 case TCG_COND_GTU: /* -> LEU */
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/qemu/tcg/aarch64/ |
H A D | tcg-target.c.inc | 369 [TCG_COND_GTU] = COND_HI, 2523 [TCG_COND_GTU] = I3616_CMHI, 2530 [TCG_COND_GTU] = I3611_CMHI,
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/qemu/tcg/loongarch64/ |
H A D | tcg-target.c.inc | 559 case TCG_COND_GTU: /* -> LEU */ 713 [TCG_COND_GTU] = { OPC_BGTU, false }
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/qemu/docs/devel/ |
H A D | tcg-ops.rst | 255 | ``TCG_COND_GTU /* unsigned */``
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/qemu/target/sh4/ |
H A D | translate.c | 736 tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
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/qemu/target/i386/tcg/ |
H A D | translate.c | 3620 gen_bndck(env, s, modrm, TCG_COND_GTU, notu); in disas_insn_old() 3727 gen_bndck(env, s, modrm, TCG_COND_GTU, cpu_bndu[reg]); in disas_insn_old()
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