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Searched refs:TCG_REG_R1 (Results 1 – 8 of 8) sorted by relevance

/qemu/tcg/ppc/
H A Dtcg-target.h36 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, enumerator
54 TCG_REG_CALL_STACK = TCG_REG_R1,
H A Dtcg-target.c.inc2844 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
2848 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
2850 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
2864 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
2867 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
2870 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
4332 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
4377 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
/qemu/tcg/tci/
H A Dtcg-target.h128 TCG_REG_R1, enumerator
H A Dtcg-target.c.inc197 TCG_REG_R1,
/qemu/tcg/arm/
H A Dtcg-target.h38 TCG_REG_R1, enumerator
H A Dtcg-target.c.inc58 TCG_REG_R1,
80 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
1421 .index = TCG_REG_R1,
1467 TCG_REG_R1, TCG_REG_R0);
1470 TCG_REG_R1, TCG_REG_R0);
1474 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
1476 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
1478 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
1483 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
2295 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
/qemu/tcg/s390x/
H A Dtcg-target.h34 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, enumerator
H A Dtcg-target.c.inc48 #define TCG_TMP0 TCG_REG_R1
351 TCG_REG_R1,
1503 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1);
3486 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);