Searched refs:TCG_REG_TMP0 (Results 1 – 5 of 5) sorted by relevance
/qemu/tcg/loongarch64/ |
H A D | tcg-target.c.inc | 540 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 628 arg2 = TCG_REG_TMP0; 856 tcg_out_opc_add_d(s, TCG_REG_TMP0, TCG_REG_TMP0, base); 858 base = TCG_REG_TMP0; 874 tcg_out_opc_add_d(s, TCG_REG_TMP0, TCG_REG_TMP0, base); 876 base = TCG_REG_TMP0; 916 .ntmp = 1, .tmp = { TCG_REG_TMP0 } 1053 h->base = TCG_REG_TMP0; 1180 base = TCG_REG_TMP0; 1233 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0); [all …]
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H A D | tcg-target.h | 84 TCG_REG_TMP0 = TCG_REG_T8, enumerator
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/qemu/tcg/riscv/ |
H A D | tcg-target.c.inc | 776 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, 862 arg2 = TCG_REG_TMP0; 1280 addr_adj = TCG_REG_TMP0; 1308 tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, 1311 tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); 1312 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, 1313 TCG_REG_TMP0, TCG_REG_TMP2); 1315 *pbase = TCG_REG_TMP0; 1334 base = TCG_REG_TMP0; 1348 base = TCG_REG_TMP0; [all …]
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H A D | tcg-target.h | 69 TCG_REG_TMP0 = TCG_REG_T6, enumerator
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/qemu/tcg/aarch64/ |
H A D | tcg-target.c.inc | 75 #define TCG_REG_TMP0 TCG_REG_X16 1056 TCGReg temp = TCG_REG_TMP0; 1420 tcg_out_insn(s, 3207, BLR, TCG_REG_TMP0); 1603 rl = TCG_REG_TMP0; 1620 al = TCG_REG_TMP0; 1661 a1 = TCG_REG_TMP0; 1700 .ntmp = 1, .tmp = { TCG_REG_TMP0 } 1780 TCG_REG_TMP0, TCG_REG_TMP0, addr_reg, 2007 ll = TCG_REG_TMP0; 2065 tcg_out_insn(s, 3207, BR, TCG_REG_TMP0); [all …]
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