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Searched refs:TCG_REG_TMP1 (Results 1 – 6 of 6) sorted by relevance

/qemu/tcg/riscv/
H A Dtcg-target.c.inc731 TCGReg th = TCG_REG_TMP1;
984 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val2);
985 val2 = TCG_REG_TMP1;
993 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val1);
994 val1 = TCG_REG_TMP1;
1012 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP1, val2, -val1);
1020 tcg_out_opc_reg(s, OPC_OR, ret, TCG_REG_TMP0, TCG_REG_TMP1);
1065 tmp = (ret == cmp1 || ret == cmp2 ? TCG_REG_TMP1 : ret);
1189 .ntmp = 3, .tmp = { TCG_REG_TMP0, TCG_REG_TMP1, TCG_REG_TMP2 }
1289 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj);
[all …]
H A Dtcg-target.h70 TCG_REG_TMP1 = TCG_REG_T5, enumerator
/qemu/tcg/ppc/
H A Dtcg-target.c.inc76 # define TCG_REG_TMP1 TCG_REG_R2
1348 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0));
1351 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0));
1512 TCGReg rs = TCG_REG_TMP1;
2363 arg = TCG_REG_TMP1;
2493 tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
2514 tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
2524 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
2580 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
2915 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, lo);
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/qemu/tcg/loongarch64/
H A Dtcg-target.h85 TCG_REG_TMP1 = TCG_REG_T7, enumerator
H A Dtcg-target.c.inc691 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */
692 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2);
993 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
998 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
1017 tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask);
1019 tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg);
1021 tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO,
1026 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0);
1043 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
1046 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0);
[all …]
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc76 #define TCG_REG_TMP1 TCG_REG_X17
1775 tcg_out_insn(s, 3314, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0,
1784 tcg_out_insn(s, 3502, ADD, 1, TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP0);
1788 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP1,
1791 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
1820 h->base = TCG_REG_TMP1;
2006 tcg_debug_assert(base != TCG_REG_TMP0 && base != TCG_REG_TMP1);
2008 lh = TCG_REG_TMP1;
3187 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);