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Searched refs:TT_TMISS (Results 1 – 3 of 3) sorted by relevance

/qemu/target/sparc/
H A Dint64_helper.c32 [TT_TMISS] = "Instruction Access MMU Miss",
221 case TT_TMISS ... TT_TMISS + 3: in sparc_cpu_do_interrupt()
H A Dcpu.h91 #define TT_TMISS 0x64 macro
H A Dmmu_helper.c716 cs->exception_index = TT_TMISS; in get_physical_address_code()