| /qemu/target/hexagon/ |
| H A D | macros.h | 225 #define fLSBOLD(VAL) ((VAL) & 1)
254 #define fNEWREG_ST(VAL) (VAL)
277 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL))
279 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL))
303 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL))
305 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
306 #define fSATH(VAL) (fSATN(16, VAL))
311 #define fSATB(VAL) (fSATN(8, VAL))
625 #define fBREV_8(VAL) revbit64(VAL)
627 #define fCL1_8(VAL) clo64(VAL)
[all …]
|
| H A D | decode.c | 27 #define fZXTN(N, M, VAL) ((VAL) & ((1LL << (N)) - 1)) argument
|
| /qemu/target/hexagon/idef-parser/ |
| H A D | macros.inc | 19 #define fLSBOLD(VAL) (fGETBIT(0, VAL))
20 #define fSATH(VAL) fSATN(16, VAL)
21 #define fSATUH(VAL) fSATUN(16, VAL)
22 #define fVSATH(VAL) fVSATN(16, VAL)
23 #define fVSATUH(VAL) fVSATUN(16, VAL)
24 #define fSATUB(VAL) fSATUN(8, VAL)
25 #define fSATB(VAL) fSATN(8, VAL)
26 #define fVSATUB(VAL) fVSATUN(8, VAL)
27 #define fVSATB(VAL) fVSATN(8, VAL)
104 #define fWRITE_P0(VAL) P0 = VAL;
[all …]
|
| /qemu/tests/tcg/hexagon/ |
| H A D | brev.c | 64 : "r"(VAL), "r"(INC) \
67 #define BREV_STORE_b(ADDR, VAL, INC) \ argument
68 BREV_STORE(b, "", ADDR, VAL, INC)
69 #define BREV_STORE_h(ADDR, VAL, INC) \ argument
70 BREV_STORE(h, "", ADDR, VAL, INC)
74 BREV_STORE(w, "", ADDR, VAL, INC)
76 BREV_STORE(d, "", ADDR, VAL, INC)
86 : "r"(VAL), "r"(INC) \
90 BREV_STORE_NEW(b, ADDR, VAL, INC)
92 BREV_STORE_NEW(h, ADDR, VAL, INC)
[all …]
|
| H A D | circ.c | 144 : "r"(START), "r"(VAL), "r"(LEN) \
147 CIRC_STORE_IMM(b, "", VAL, ADDR, START, LEN, INC)
149 CIRC_STORE_IMM(h, "", VAL, ADDR, START, LEN, INC)
153 CIRC_STORE_IMM(w, "", VAL, ADDR, START, LEN, INC)
155 CIRC_STORE_IMM(d, "", VAL, ADDR, START, LEN, INC)
167 : "r"(START), "r"(VAL), "r"(LEN) \
170 CIRC_STORE_NEW_IMM(b, VAL, ADDR, START, LEN, INC)
172 CIRC_STORE_NEW_IMM(h, VAL, ADDR, START, LEN, INC)
174 CIRC_STORE_NEW_IMM(w, VAL, ADDR, START, LEN, INC)
185 "r"(VAL) \
[all …]
|
| H A D | v69_hvx.c | 28 #define fVROUND(VAL, SHAMT) \ argument
29 ((VAL) + (((SHAMT) > 0) ? (1LL << ((SHAMT) - 1)) : 0))
31 #define fVSATUB(VAL) \ argument
32 ((((VAL) & 0xffLL) == (VAL)) ? \
33 (VAL) : \
34 ((((int32_t)(VAL)) < 0) ? 0 : 0xff))
36 #define fVSATUH(VAL) \ argument
37 ((((VAL) & 0xffffLL) == (VAL)) ? \
38 (VAL) : \
39 ((((int32_t)(VAL)) < 0) ? 0 : 0xffff))
|
| /qemu/target/hexagon/imported/ |
| H A D | macros.def | 118 ((VAL) & 1),
142 (!fLSBOLD(VAL)),
217 ((fSXTN(N,64,VAL) == (VAL)) ? (VAL) : fSATVALN(N,VAL)),
222 ((fSXTN(N,64,VAL) == (VAL)) ? (VAL) : fVSATVALN(N,VAL)),
256 ((fZXTN(N,64,VAL) == (VAL)) ? (VAL) : fVSATUVALN(N,VAL)),
262 ((fZXTN(N,64,VAL) == (VAL)) ? (VAL) : fSATUVALN(N,VAL)),
268 (fSATN(16,VAL)),
275 (fSATUN(16,VAL)),
294 (fSATUN(8,VAL)),
299 (fSATN(8,VAL)),
[all …]
|
| /qemu/target/hexagon/mmvec/ |
| H A D | macros.h | 48 #define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \
50 env->vtcm_log.data.ub[IDX] = (VAL); \
59 #define fNOTQ(VAL) \
64 _ret.ud[_i_] = ~VAL.ud[_i_]; \
96 uint32_t __TMP = (VAL); \
100 #define fSETQBIT(REG, BITNO, VAL) fSETQBITS(REG, 1, 1, BITNO, VAL)
339 #define fVNOROUND(VAL, SHAMT) VAL
340 #define fVNOSAT(VAL) VAL
341 #define fVROUND(VAL, SHAMT) \
350 #define fGET10BIT(COE, VAL, POS) \
[all …]
|
| /qemu/hw/misc/ |
| H A D | xlnx-versal-trng.c | 104 FIELD(RESET, VAL, 0, 1)
106 FIELD(OSC_EN, VAL, 0, 1)
145 if (ARRAY_FIELD_EX32(s->regs, RESET, VAL)) { in trng_in_reset()
168 if (!ARRAY_FIELD_EX32(s->regs, OSC_EN, VAL)) { in trng_trss_enabled()
487 if (!ARRAY_FIELD_EX32(s->regs, RESET, VAL) && in trng_reset_prew()
488 FIELD_EX32(val64, RESET, VAL)) { in trng_reset_prew()
|
| /qemu/target/hexagon/imported/mmvec/ |
| H A D | macros.def | 36 …({mmqreg_t _ret = {0}; int _i_; for (_i_ = 0; _i_ < fVECSIZE()/64; _i_++) _ret.ud[_i_] = ~VAL.ud[_…
59 COE = (((((fGETUBYTE(3,VAL) >> (2 * POS)) & 3) << 8) | fGETUBYTE(POS,VAL)) << 6);
122 size4u_t __TMP = (VAL);
130 fSETQBITS(REG,1,1,BITNO,VAL),
816 VAL,
820 VAL,
825 ((VAL) + (((SHAMT)>0)?(1LL<<((SHAMT)-1)):0)),
|
| /qemu/target/arm/ |
| H A D | cpu.h | 3130 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ argument
3131 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
3132 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ argument
3133 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL))
3134 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ argument
3135 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
3136 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ argument
3137 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
3138 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ argument
3139 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
|
| /qemu/hw/nvram/ |
| H A D | xlnx-bbram.c | 71 FIELD(BBRAM_MSW_LOCK, VAL, 0, 1)
83 return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0; in bbram_msw_locked()
|
| /qemu/hw/char/ |
| H A D | ibex_uart.c | 74 REG32(VAL, 0x2C)
|