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Searched refs:VC_ENDC_WATCH0_DATA0 (Results 1 – 2 of 2) sorted by relevance

/qemu/hw/intc/
H A Dpnv_xive2_regs.h300 #define VC_ENDC_WATCH0_DATA0 0x520 macro
H A Dpnv_xive2.c344 cpu_to_be64(xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i]); in pnv_xive2_end_update()
365 xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i] = in pnv_xive2_end_cache_load()
1012 case VC_ENDC_WATCH0_DATA0: in pnv_xive2_ic_vc_read()
1108 case VC_ENDC_WATCH0_DATA0: in pnv_xive2_ic_vc_write()