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Searched refs:XCHAL_HAVE_PIF_WR_RESP (Results 1 – 2 of 2) sorted by relevance

/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h273 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ macro
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h351 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ macro