Searched refs:XI1 (Results 1 – 3 of 3) sorted by relevance
78 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; in r4k_fill_tlb()120 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; in r4k_helper_tlbwi() local140 XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; in r4k_helper_tlbwi()153 (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { in r4k_helper_tlbwi()268 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) | in r4k_helper_tlbr()421 if (access_type == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) { in r4k_map_address()433 if (!(n ? tlb->XI1 : tlb->XI0)) { in r4k_map_address()
156 v->XI1 = (flags >> 12) & 1; in get_tlb()173 (v->XI1 << 12) | in put_tlb()
134 unsigned int XI1:1; member