Searched refs:amr (Results 1 – 6 of 6) sorted by relevance
95 filter->can_mask = (uint32_t)amr[0] << 21; in can_sja_single_filter()97 filter->can_mask |= (uint32_t)amr[2] << 5; in can_sja_single_filter()98 filter->can_mask |= (uint32_t)amr[3] >> 3; in can_sja_single_filter()100 if (!(amr[3] & 4)) { in can_sja_single_filter()110 filter->can_mask = (uint32_t)amr[0] << 3; in can_sja_single_filter()111 filter->can_mask |= (uint32_t)amr[1] >> 5; in can_sja_single_filter()113 if (!(amr[1] & 0x10)) { in can_sja_single_filter()127 filter->can_mask = (uint32_t)amr[0] << 21; in can_sja_dual_filter()137 filter->can_mask = (uint32_t)amr[0] << 3; in can_sja_dual_filter()138 filter->can_mask |= (uint32_t)amr[1] >> 5; in can_sja_dual_filter()[all …]
64 int amr = env->spr[SPR_AMR] >> 62; /* We only care about key0 AMR63:62 */ in ppc_radix64_get_prot_amr() local67 return (amr & 0x2 ? 0 : PAGE_WRITE) | /* Access denied if bit is set */ in ppc_radix64_get_prot_amr()68 (amr & 0x1 ? 0 : PAGE_READ) | in ppc_radix64_get_prot_amr()
103 val = s->amr; in lasi_chip_read_with_attrs()183 s->amr = val; in lasi_chip_write_with_attrs()219 VMSTATE_UINT32(amr, LasiState),
73 uint32_t amr; member
463 uint64_t amr; member
191 save->amr = env->spr[SPR_AMR]; in nested_save_state()290 env->spr[SPR_AMR] = load->amr; in nested_load_state()979 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMR, amr),