Searched refs:b10 (Results 1 – 16 of 16) sorted by relevance
/qemu/tests/tcg/ppc64/ |
H A D | vector.c | 40 assert(result_wi == 0b10); in main()
|
/qemu/pc-bios/s390-ccw/ |
H A D | scsi.h | 136 uint8_t b10; member
|
/qemu/target/ppc/ |
H A D | power8-pmu-regs.c.inc | 36 * Write access is granted for PMCC values 0b10 and 0b11. Userspace 148 * When MMCR0[PMCC] is set to 0b10 or 0b11, providing
|
/qemu/tests/tcg/xtensa/ |
H A D | test_fp1.S | 52 test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na, FSR_V /* -SNaN ord */
|
/qemu/target/riscv/ |
H A D | cpu_bits.h | 876 #define SEED_OPST_ES16 (0b10 << 30)
|
/qemu/docs/specs/ |
H A D | ppc-xive.rst | 152 ``0b10``) is for the operating system, ring 2 view. The fourth (page
|
/qemu/target/xtensa/core-test_mmuhifi_c3/ |
H A D | gdb-config.c.inc | 162 XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
|
/qemu/target/xtensa/core-test_kc705_be/ |
H A D | gdb-config.c.inc | 195 XTREG(150,618, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
|
/qemu/target/xtensa/core-de233_fpu/ |
H A D | gdb-config.c.inc | 199 XTREG(150,634, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
|
/qemu/tests/qtest/ |
H A D | npcm7xx_emc-test.c | 601 (0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner = 10: emc */ in init_rx_desc()
|
/qemu/target/mips/tcg/ |
H A D | msa_translate.c | 111 [DF_WORD] = {5, 2, 0b10},
|
/qemu/target/arm/tcg/ |
H A D | neon-dp.decode | 388 # grouping ([23,4]=0b10), bits [21:20] are either part of the opcode
|
/qemu/target/xtensa/core-dsp3400/ |
H A D | gdb-config.c.inc | 330 XTREG(241,2054, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
|
/qemu/tests/avocado/acpi-bits/bits-tests/ |
H A D | smbios.py2 | 598 0b10: 'Varies with Memory Address', 606 0b10: 'Reserved', 1495 0b10: 'System utilities', 2044 0b10: 'Interface registers are on 16-byte boundaries',
|
/qemu/target/arm/ |
H A D | ptw.c | 322 case 0b10: /* outer shareable */ in granule_protection_check() 343 case 0b10: /* 16KB */ in granule_protection_check()
|
/qemu/hw/misc/ |
H A D | stm32l4x5_rcc.c | 467 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b10 && in rcc_update_cr_register()
|