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Searched refs:bar (Results 1 – 25 of 114) sorted by relevance

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/qemu/tests/qtest/libqos/
H A Dvirtio-pci-modern.c45 qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + in get_features()
52 qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + in get_features()
284 qpci_io_writew(d->pdev, d->bar, d->common_cfg_offset + in set_config_vector()
298 qpci_io_writew(d->pdev, d->bar, d->common_cfg_offset + in set_queue_vector()
370 *bar = qpci_config_readb(dev->pdev, in find_structure()
388 uint8_t bar; in probe_device_layout() local
401 dev->bar_idx = bar; in probe_device_layout()
407 g_assert_cmphex(bar, ==, dev->bar_idx); in probe_device_layout()
413 if (!find_structure(dev, VIRTIO_PCI_CAP_ISR_CFG, &bar, in probe_device_layout()
417 g_assert_cmphex(bar, ==, dev->bar_idx); in probe_device_layout()
[all …]
H A Dvirtio-pci.c45 return qpci_io_readb(dev->pdev, dev->bar, CONFIG_BASE(dev) + off); in qvirtio_pci_config_readb()
60 value = qpci_io_readw(dev->pdev, dev->bar, CONFIG_BASE(dev) + off); in qvirtio_pci_config_readw()
72 value = qpci_io_readl(dev->pdev, dev->bar, CONFIG_BASE(dev) + off); in qvirtio_pci_config_readl()
84 val = qpci_io_readq(dev->pdev, dev->bar, CONFIG_BASE(dev) + off); in qvirtio_pci_config_readq()
113 return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS); in qvirtio_pci_get_status()
119 qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS, status); in qvirtio_pci_set_status()
186 qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_SEL, index); in qvirtio_pci_queue_select()
192 return qpci_io_readw(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NUM); in qvirtio_pci_get_queue_size()
200 qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_PFN, pfn); in qvirtio_pci_set_queue_address()
306 d->bar = qpci_iomap(d->pdev, d->bar_idx, NULL); in qvirtio_pci_device_enable()
[all …]
H A Dusb.c19 void qusb_pci_init_one(QPCIBus *pcibus, struct qhc *hc, uint32_t devfn, int bar) in qusb_pci_init_one() argument
24 hc->bar = qpci_iomap(hc->dev, bar, NULL); in qusb_pci_init_one()
34 uint16_t value = qpci_io_readw(hc->dev, hc->bar, 0x10 + 2 * port); in uhci_port_test()
H A Dusb.h8 QPCIBar bar; member
12 uint32_t devfn, int bar);
H A Dpci.c527 QPCIBar bar; in qpci_iomap() local
560 bar.is_io = true; in qpci_iomap()
571 bar.is_io = false; in qpci_iomap()
576 bar.addr = loc; in qpci_iomap()
577 return bar; in qpci_iomap()
580 void qpci_iounmap(QPCIDevice *dev, QPCIBar bar) in qpci_iounmap() argument
587 QPCIBar bar = { .addr = addr, .is_io = true }; in qpci_legacy_iomap() local
588 return bar; in qpci_legacy_iomap()
/qemu/tests/qtest/
H A Dnvme-test.c54 QPCIBar bar; in nvmetest_oob_cmb_test() local
57 bar = qpci_iomap(pdev, 2, NULL); in nvmetest_oob_cmb_test()
59 qpci_io_writel(pdev, bar, 0, 0xccbbaa99); in nvmetest_oob_cmb_test()
60 g_assert_cmpint(qpci_io_readb(pdev, bar, 0), ==, 0x99); in nvmetest_oob_cmb_test()
64 qpci_io_writel(pdev, bar, cmb_bar_size - 1, 0x44332211); in nvmetest_oob_cmb_test()
74 QPCIBar bar; in nvmetest_reg_read_test() local
79 bar = qpci_iomap(pdev, 0, NULL); in nvmetest_reg_read_test()
81 cap_lo = qpci_io_readl(pdev, bar, 0x0); in nvmetest_reg_read_test()
84 cap_hi = qpci_io_readl(pdev, bar, 0x4); in nvmetest_reg_read_test()
87 cap = qpci_io_readq(pdev, bar, 0x0); in nvmetest_reg_read_test()
[all …]
H A Dpvpanic-pci-test.c28 QPCIBar bar; in test_panic_nopause() local
34 bar = qpci_iomap(dev, 0, NULL); in test_panic_nopause()
36 qpci_memread(dev, bar, 0, &val, sizeof(val)); in test_panic_nopause()
40 qpci_memwrite(dev, bar, 0, &val, sizeof(val)); in test_panic_nopause()
61 QPCIBar bar; in test_panic() local
67 bar = qpci_iomap(dev, 0, NULL); in test_panic()
69 qpci_memread(dev, bar, 0, &val, sizeof(val)); in test_panic()
73 qpci_memwrite(dev, bar, 0, &val, sizeof(val)); in test_panic()
H A Dtulip-test.c52 QPCIBar bar; in tulip_large_tx() local
59 bar = qpci_iomap(dev, 0, NULL); in tulip_large_tx()
71 qpci_io_writel(dev, bar, 0x20, context_pa); in tulip_large_tx()
72 qpci_io_writel(dev, bar, 0x30, CSR6_ST); in tulip_large_tx()
H A Dmegasas-test.c52 QPCIBar bar; in megasas_pd_get_info_fuzz() local
58 bar = qpci_iomap(dev, 0, NULL); in megasas_pd_get_info_fuzz()
71 qpci_io_writel(dev, bar, 0x40, context_pa); in megasas_pd_get_info_fuzz()
H A Dufs-test.c35 QPCIBar bar; member
47 return qpci_io_readl(&ufs->dev, ufs->bar, offset); in ufs_rreg()
52 qpci_io_writel(&ufs->dev, ufs->bar, offset, value); in ufs_wreg()
262 ufs->bar = qpci_iomap(&ufs->dev, 0, NULL); in ufs_init()
373 qpci_iounmap(&ufs->dev, ufs->bar); in ufs_exit()
404 ufs->bar = qpci_iomap(&ufs->dev, 0, NULL); in ufstest_reg_read()
412 qpci_iounmap(&ufs->dev, ufs->bar); in ufstest_reg_read()
/qemu/hw/misc/macio/
H A Dmacio.c87 MemoryRegion *bar = sysbus_mmio_get_region(sbd, 0); in macio_bar_setup() local
89 memory_region_add_subregion(&s->bar, 0x13000, bar); in macio_bar_setup()
102 memory_region_add_subregion(&s->bar, 0x08000, in macio_common_realize()
155 memory_region_add_subregion(&s->bar, 0x0, in macio_oldworld_realize()
164 memory_region_add_subregion(&s->bar, 0x16000, in macio_oldworld_realize()
176 memory_region_add_subregion(&s->bar, 0x60000, in macio_oldworld_realize()
278 memory_region_add_subregion(&s->bar, 0x40000, in macio_newworld_realize()
316 memory_region_add_subregion(&s->bar, 0x50, in macio_newworld_realize()
329 memory_region_add_subregion(&s->bar, 0x16000, in macio_newworld_realize()
344 memory_region_add_subregion(&s->bar, 0x16000, in macio_newworld_realize()
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/qemu/hw/vfio/
H A Dpci.c1298 int bar; in vfio_pci_write_config() local
1300 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { in vfio_pci_write_config()
1301 old_addr[bar] = pdev->io_regions[bar].addr; in vfio_pci_write_config()
1306 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { in vfio_pci_write_config()
1307 if (old_addr[bar] != pdev->io_regions[bar].addr && in vfio_pci_write_config()
1751 bar->size = bar->region.size; in vfio_bar_prepare()
1786 pci_register_bar(&vdev->pdev, nr, bar->type, bar->mr); in vfio_bar_register()
2624 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { in vfio_pci_load_config()
2625 old_addr[bar] = pdev->io_regions[bar].addr; in vfio_pci_load_config()
2636 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { in vfio_pci_load_config()
[all …]
H A Dpci-quirks.c94 uint8_t bar; member
196 uint8_t bar; member
464 window->bar = nr; in vfio_probe_ati_bar4_quirk()
506 mirror->bar = nr; in vfio_probe_ati_bar2_quirk()
805 window->bar = nr; in vfio_probe_nvidia_bar5_quirk()
958 mirror->bar = nr; in vfio_probe_nvidia_bar0_quirk()
979 mirror->bar = nr; in vfio_probe_nvidia_bar0_quirk()
1268 VFIOBAR *bar = &vdev->bars[nr]; in vfio_bar_quirk_exit() local
1285 VFIOBAR *bar = &vdev->bars[nr]; in vfio_bar_quirk_finalize() local
1288 while (!QLIST_EMPTY(&bar->quirks)) { in vfio_bar_quirk_finalize()
[all …]
/qemu/target/ppc/translate/
H A Dmisc-impl.c.inc26 TCGBar bar = TCG_MO_ALL;
38 tcg_gen_mb(bar | TCG_BAR_SC);
57 bar = TCG_MO_ST_ST;
61 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
77 tcg_gen_mb(bar | TCG_BAR_SC);
84 TCGBar bar = TCG_MO_ALL;
94 tcg_gen_mb(bar | TCG_BAR_SC);
140 bar = TCG_MO_ST_LD;
144 tcg_gen_mb(bar | TCG_BAR_SC);
/qemu/hw/pci-host/
H A Dpnv_phb3_pbcq.c61 uint64_t bar, mask, size; in pnv_pbcq_update_map() local
91 bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] >> 14; in pnv_pbcq_update_map()
95 memory_region_add_subregion(get_system_memory(), bar, &pbcq->mmbar0); in pnv_pbcq_update_map()
96 pbcq->mmio0_base = bar; in pnv_pbcq_update_map()
101 bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] >> 14; in pnv_pbcq_update_map()
105 memory_region_add_subregion(get_system_memory(), bar, &pbcq->mmbar1); in pnv_pbcq_update_map()
106 pbcq->mmio1_base = bar; in pnv_pbcq_update_map()
111 bar = pbcq->nest_regs[PBCQ_NEST_PHB_BAR] >> 14; in pnv_pbcq_update_map()
114 memory_region_add_subregion(get_system_memory(), bar, &pbcq->phbbar); in pnv_pbcq_update_map()
/qemu/hw/pci-bridge/
H A Dpci_bridge_dev.c45 MemoryRegion bar; member
67 memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", in pci_bridge_dev_realize()
69 err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0, errp); in pci_bridge_dev_realize()
112 PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar); in pci_bridge_dev_realize()
122 shpc_cleanup(dev, &bridge_dev->bar); in pci_bridge_dev_realize()
138 shpc_cleanup(dev, &bridge_dev->bar); in pci_bridge_dev_exitfn()
/qemu/docs/specs/
H A Dstandard-vga.rst32 Reserved (so we have the option to make the framebuffer bar 64bit).
35 MMIO bar, 4096 bytes in size (QEMU 1.3+)
48 Doesn't apply to the legacy-free pci variant, use the MMIO bar instead.
66 The pci variant used to mirror the framebuffer bar here, QEMU 0.14+
H A Dpci-serial.rst21 IO bar, 8 bytes long, with the 16550 UART mapped to it.
34 IO bar, with two or four 16550 UARTs mapped after each other.
/qemu/tests/tcg/x86_64/
H A Dtest-1648.c7 void bar(void) in bar() function
20 bar(); in foo()
/qemu/hw/xen/
H A Dxen_pt.c489 pci_register_bar(&s->dev, i, type, &s->bar[i]); in xen_pt_register_regions()
532 if (mr == &s->bar[i]) { in xen_pt_bar_from_region()
594 int bar = -1; in xen_pt_region_update() local
604 bar = xen_pt_bar_from_region(s, mr); in xen_pt_region_update()
605 if (bar == -1 && (!s->msix || &s->msix->mmio != mr)) { in xen_pt_region_update()
617 args.type = d->io_regions[bar].type; in xen_pt_region_update()
623 bar, sec->offset_within_address_space, in xen_pt_region_update()
627 if (d->io_regions[bar].type & PCI_BASE_ADDRESS_SPACE_IO) { in xen_pt_region_update()
629 uint32_t machine_port = s->bases[bar].access.pio_base; in xen_pt_region_update()
640 pcibus_t machine_addr = s->bases[bar].access.maddr in xen_pt_region_update()
[all …]
/qemu/tests/decode/
H A Dsucc_named_field.decode18 @bar 00000010 ........ ........ ........ &imm_a alpha=4
19 i3 ........ 00000000 ........ ........ @bar imm=%foo
/qemu/include/hw/pci/
H A Dshpc.h41 int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar,
43 void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar);
/qemu/hw/acpi/
H A Derst.c189 pcibus_t bar; member
219 gas.address = (uint64_t)(e->bar + e->register_offset); in build_serialization_instruction()
245 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
251 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
257 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
263 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
269 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
275 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
281 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
/qemu/hw/nvme/
H A Dctrl.c7151 stl_le_p(&n->bar.intms, 0); in nvme_ctrl_reset()
7152 stl_le_p(&n->bar.intmc, 0); in nvme_ctrl_reset()
7153 stl_le_p(&n->bar.cc, 0); in nvme_ctrl_reset()
7320 n->bar.intmc = n->bar.intms; in nvme_write_bar()
7333 n->bar.intmc = n->bar.intms; in nvme_write_bar()
7443 n->bar.cmbsz = 0; in nvme_write_bar()
7444 n->bar.cmbloc = 0; in nvme_write_bar()
7732 if (addr < sizeof(n->bar)) { in nvme_mmio_write()
7991 stq_le_p(&n->bar.cap, cap); in nvme_init_cmb()
8293 stq_le_p(&n->bar.cap, cap); in nvme_init_ctrl()
[all …]
/qemu/include/standard-headers/linux/
H A Dvirtio_pci.h125 uint8_t bar; /* Where to find it. */ member
280 uint8_t bar; /* BAR of the member or the owner device */ member

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